[SPIRV] Add legalization for long vectors

[s-perron]

This patch introduces the necessary infrastructure to legalize vector
operations on vectors that are longer than what the SPIR-V target
supports. For instance, shaders only support vectors up to 4 elements.

The legalization is done by splitting the long vectors into smaller
vectors of a legal size.

Specifically, this patch does the following:

• Introduces vectorElementCountIsGreaterThan and
  vectorElementCountIsLessThanOrEqualTo legality predicates.
• Adds legalization rules for G_SHUFFLE_VECTOR, G_EXTRACT_VECTOR_ELT,
  G_BUILD_VECTOR, G_CONCAT_VECTORS, G_SPLAT_VECTOR, and
  G_UNMERGE_VALUES.
• Handles G_BITCAST of long vectors by converting them to
  @llvm.spv.bitcast intrinsics which are then legalized.
• Updates selectUnmergeValues to handle extraction of both scalars
  and vectors from a larger vector, using OpCompositeExtract and
  OpVectorShuffle respectively.
• Adds a test case to verify the legalization of a bitcast between
  a <8 x i32> and <4 x f64>, which is a pattern generated by
  HLSL's asuint and asdouble intrinsics.

Fixes #165444

[github-actions]

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp --diff_from_common_commit

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View the diff from clang-format here.

diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index 7bd68dfd2..6ae73a11e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -108,8 +108,8 @@ static SPIRVType *deduceTypeFromSingleOperand(MachineInstr *I,
       Register ResVReg = I->getOperand(0).getReg();
       const LLT &ResLLT = MIB.getMRI()->getType(ResVReg);
       if (ResLLT.isVector())
-        return GR->getOrCreateSPIRVVectorType(
-            CompType, ResLLT.getNumElements(), MIB, false);
+        return GR->getOrCreateSPIRVVectorType(CompType, ResLLT.getNumElements(),
+                                              MIB, false);
       return CompType;
     }
   }