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[AMDGPU] Support bfloat comparison for ballot intrinsic #165495

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Merged
changpeng merged 2 commits into from
Oct 30, 2025
Merged

[AMDGPU] Support bfloat comparison for ballot intrinsic #165495

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76e4afb
[AMDGPU] Support bfloat comparison for ballot intrinsic
changpeng Oct 29, 2025
a84e5e8
Fix a typo
changpeng Oct 29, 2025
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10 changes: 8 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7035,9 +7035,15 @@ static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,
SDLoc SL(N);

if (Src.getOpcode() == ISD::SETCC) {
SDValue Op0 = Src.getOperand(0);
SDValue Op1 = Src.getOperand(1);
// Need to expand bfloat to float for comparison (setcc).
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@jayfoad jayfoad Oct 29, 2025

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Surely generic legalization of ISD::SETCC should already promote bf16 to f32? And if that doesn't work because the ISD::SETCC hasn't been legalized yet, can't we just use the same generic machinery to promote bf16 AMDGPUISD::SETCC to f32?

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@changpeng changpeng Oct 29, 2025

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Yes, legalization of ISD::SETCC correctly promotes bf16 to f32. But apparently the ballot intrinsic is lowered to AMDGPUISD::SETCC here, so we have to promote bf16 to f32. What is the "generic machinery to promote bf16"?

Look at the "lowerFCMPIntrinsic" above this function, a similar approach was sued to promote f16 to f32 when f16 is not legal.

if (Op0.getValueType() == MVT::bf16) {
Op0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Op0);
Op1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Op1);
}
// (ballot (ISD::SETCC ...)) -> (AMDGPUISD::SETCC ...)
return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0),
Src.getOperand(1), Src.getOperand(2));
return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Op0, Op1, Src.getOperand(2));
}
if (const ConstantSDNode *Arg = dyn_cast<ConstantSDNode>(Src)) {
// (ballot 0) -> 0
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21 changes: 21 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
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Expand Up @@ -591,3 +591,24 @@ exit:
store i32 %ballot, ptr addrspace(1) %out
ret void
}

define amdgpu_cs i32 @compare_bfloats(bfloat %x, bfloat %y) {
; GFX10-LABEL: compare_bfloats:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_cmp_gt_f32_e64 s0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: compare_bfloats:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b16_e32 v2.l, 0
; GFX11-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-NEXT: v_mov_b16_e32 v1.h, v0.l
; GFX11-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v1, v2
; GFX11-NEXT: ; return to shader part epilog
%cmp = fcmp ogt bfloat %x, %y
%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
ret i32 %ballot
}
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
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Expand Up @@ -557,3 +557,15 @@ exit:
store i64 %ballot, ptr addrspace(1) %out
ret void
}

define amdgpu_cs i64 @compare_bfloats(bfloat %x, bfloat %y) {
; CHECK-LABEL: compare_bfloats:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; CHECK-NEXT: v_cmp_gt_f32_e64 s[0:1], v0, v1
; CHECK-NEXT: ; return to shader part epilog
%cmp = fcmp ogt bfloat %x, %y
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
ret i64 %ballot
}