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[AMDGPU] Mark WMMA machine instructions as convergent #165602

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Nov 4, 2025
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[AMDGPU] Mark WMMA machine instructions as convergent #165602

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14454de
[AMDGPU] WMMA convergent flag fix
mssefat Oct 29, 2025
45b5989
[AMDGPU] WMMA convergent flag fix
mssefat Oct 29, 2025
482bcd2
[AMDGPU] WMMA convergent flag fix
mssefat Oct 31, 2025
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10 changes: 6 additions & 4 deletions llvm/lib/Target/AMDGPU/VOP3PInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1707,7 +1707,7 @@ multiclass WMMAInstGFX12<string Instr, VOP3PWMMA_Profile WMMAProfile, string Pse
defvar WMMAConstraints2Addr = !if(DiffVdstSrc2, "@earlyclobber $vdst", "@earlyclobber $vdst,$vdst = $src2");
defvar WMMAConstraints3Addr = "@earlyclobber $vdst";

let Mnemonic = Instr, mayRaiseFPException = 0, ReadsModeReg = 0 in {
let Mnemonic = Instr, mayRaiseFPException = 0, ReadsModeReg = 0, isConvergent = 1 in {
let Constraints = WMMAConstraints2Addr, isConvertibleToThreeAddress = 1 in
def _twoaddr : VOP3P_Pseudo<Instr, WMMAProfile>, WMMAInstInfo {
let PseudoInstr = Instr#PseudoInstrSuffix;
Expand All @@ -1734,7 +1734,7 @@ multiclass SWMMACInstGFX12<string Instr, VOP3PWMMA_Profile WMMAProfile, string P
let mayRaiseFPException = 0;
let ReadsModeReg = 0;
let AsmMatchConverter = "cvtSWMMAC";

let isConvergent = 1;
let Constraints = "@earlyclobber $vdst,$vdst = $srcTiedDef";
}
}
Expand Down Expand Up @@ -1906,8 +1906,10 @@ defm V_WMMA_SCALE_F32_32X16X128_F4_w32 : WMMAInstGFX12<"v_wmma_scale_f32_32x16
defm V_WMMA_SCALE16_F32_32X16X128_F4_w32 : WMMAInstGFX12<"v_wmma_scale16_f32_32x16x128_f4", F32_32X16X128_F4_SCALE16_w32, "_w32">;
} // End is_wmma_xdl = 1.

defm V_WMMA_LD_SCALE_PAIRED_B32 : VOP3PInst<"v_wmma_ld_scale_paired_b32", VOP_WMMA_LD_SCALE<i32, VCSrc_b32_Lo256>>;
defm V_WMMA_LD_SCALE16_PAIRED_B64 : VOP3PInst<"v_wmma_ld_scale16_paired_b64", VOP_WMMA_LD_SCALE<i64, VCSrc_b64_Lo256>>;
let isConvergent = 1 in {
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@bcahoon bcahoon Oct 30, 2025

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Should we move isConvergent VOP_WMMA_LD_SCALE?

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@mssefat mssefat Oct 31, 2025

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I think we should avoid moving isConvergent = 1 directly into VOP_WMMA_LD_SCALE since it extends a profile class and isConvergent is an instruction property.

Instead we can create VOP3PInst_WMMA_LD that extends VOP3PInst specifically for WMMA_LD_SCALE_PAIRED instructions:

multiclass VOP3PInst_WMMA_LD<string OpName, VOPProfile P, SDPatternOperator node = null_frag> {
  let isConvergent = 1 in {
    defm NAME : VOP3PInst<OpName, P, node>;
  }
}

Then we can use it for WMMA LD_SCALE_PAIRED instructions:

defm V_WMMA_LD_SCALE_PAIRED_B32   : VOP3PInst_WMMA_LD<"v_wmma_ld_scale_paired_b32",   VOP_WMMA_LD_SCALE<i32, VCSrc_b32_Lo256>>;
defm V_WMMA_LD_SCALE16_PAIRED_B64 : VOP3PInst_WMMA_LD<"v_wmma_ld_scale16_paired_b64", VOP_WMMA_LD_SCALE16<i64, VCSrc_b64_Lo256>>;

Please let me know if this looks better to you or you suggest me to stick with the existing one.

defm V_WMMA_LD_SCALE_PAIRED_B32 : VOP3PInst<"v_wmma_ld_scale_paired_b32", VOP_WMMA_LD_SCALE<i32, VCSrc_b32_Lo256>>;
defm V_WMMA_LD_SCALE16_PAIRED_B64 : VOP3PInst<"v_wmma_ld_scale16_paired_b64", VOP_WMMA_LD_SCALE<i64, VCSrc_b64_Lo256>>;
}
} // End SubtargetPredicate = isGFX125xOnly
} // End WaveSizePredicate = isWave32

Expand Down
42 changes: 42 additions & 0 deletions llvm/test/CodeGen/AMDGPU/wmma-gfx12-convergent.mir
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@@ -0,0 +1,42 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx12-generic -run-pass=machine-sink %s -o - | FileCheck %s

---
name: wmma_test
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: wmma_test
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: early-clobber %3:vreg_256 = V_WMMA_F32_16X16X16_F16_w32_threeaddr 8, [[DEF]], 8, [[DEF1]], 8, 0, 0, 0, implicit $exec
; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY %3.sub1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; CHECK-NEXT: S_ENDPGM 0
bb.0:
%0:vreg_128 = IMPLICIT_DEF
%1:vreg_128 = IMPLICIT_DEF
%2:sreg_32 = IMPLICIT_DEF
early-clobber %3:vreg_256 = V_WMMA_F32_16X16X16_F16_w32_threeaddr 8, %0:vreg_128, 8, %1:vreg_128, 8, 0, 0, 0, implicit $exec
%4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.1

bb.1:
%5:vreg_256 = COPY %3.sub1:vreg_256

bb.2:
SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM 0

...