[SPIRV] Enable OpenCL max_work_group_size translation via `SPV_INTEL_kernel_attributes` #165891

AlexVlx · 2025-10-31T17:52:36Z

This adds BE support for the SPV_INTEL_kernel_attributes extension. The extension is necessary to encode the rather useful max_work_group_size kernel attribute, via OpExecutionMode MaxWorkgroupSizeINTEL, which is the only Execution Mode added by the extension that this patch adds full processing for. Future patches will add the other Execution Modes and Capabilities. The test is adapted from the equivalent Translator test; it depends on #165815.

… HIPSTDPAR runtime component.

llvmbot · 2025-10-31T17:53:28Z

@llvm/pr-subscribers-backend-spir-v

Author: Alex Voicu (AlexVlx)

Changes

This adds BE support for the SPV_INTEL_kernel_attributes extension. The extension is necessary to encode the rather useful max_work_group_size kernel attribute, via OpExecutionMode MaxWorkgroupSizeINTEL, which is the only Execution Mode added by the extension that this patch adds full processing for. Future patches will add the other Execution Modes and Capabilities. The test is adapted from the equivalent Translator test; it depends on #165815.

Full diff: https://github.com/llvm/llvm-project/pull/165891.diff

5 Files Affected:

(modified) llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp (+7-1)
(modified) llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp (+3-1)
(modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+5)
(modified) llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td (+11-1)
(added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_kernel_attributes/max_work_group_size.ll (+32)

diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
index 640b014646f36..46d0a6724a74b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
@@ -577,6 +577,11 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
     if (MDNode *Node = F.getMetadata("intel_reqd_sub_group_size"))
       outputExecutionModeFromMDNode(FReg, Node,
                                     SPIRV::ExecutionMode::SubgroupSize, 0, 0);
+    if (MDNode *Node = F.getMetadata("max_work_group_size")) {
+      if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_kernel_attributes))
+        outputExecutionModeFromMDNode(
+            FReg, Node, SPIRV::ExecutionMode::MaxWorkgroupSizeINTEL, 3, 1);
+    }
     if (MDNode *Node = F.getMetadata("vec_type_hint")) {
       MCInst Inst;
       Inst.setOpcode(SPIRV::OpExecutionMode);
@@ -628,7 +633,8 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
             // Check if the constant is int32, if not skip it.
             const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
             MachineInstr *TypeMI = MRI.getVRegDef(MI->getOperand(1).getReg());
-            if (!TypeMI || TypeMI->getOperand(1).getImm() != 32)
+            if (!TypeMI || !TypeMI->getOperand(1).isImm() ||
+                TypeMI->getOperand(1).getImm() != 32)
               continue;
 
             ConstZero = MI;
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 96f5dee21bc2a..f0558ebcb6681 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -155,7 +155,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
         {"SPV_INTEL_predicated_io",
          SPIRV::Extension::Extension::SPV_INTEL_predicated_io},
         {"SPV_KHR_maximal_reconvergence",
-         SPIRV::Extension::Extension::SPV_KHR_maximal_reconvergence}};
+         SPIRV::Extension::Extension::SPV_KHR_maximal_reconvergence},
+        {"SPV_INTEL_kernel_attributes",
+         SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes}};
 
 bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
                                   StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index f7cdfcb65623b..5db592b2c097e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -2181,6 +2181,11 @@ static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI,
       MAI.Reqs.getAndAddRequirements(
           SPIRV::OperandCategory::ExecutionModeOperand,
           SPIRV::ExecutionMode::SubgroupSize, ST);
+    if (F.getMetadata("max_work_group_size"))
+      MAI.Reqs.getAndAddRequirements(
+          SPIRV::OperandCategory::ExecutionModeOperand,
+          SPIRV::ExecutionMode::MaxWorkgroupSizeINTEL,
+          ST);
     if (F.getMetadata("vec_type_hint"))
       MAI.Reqs.getAndAddRequirements(
           SPIRV::OperandCategory::ExecutionModeOperand,
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 7d08b29a51a6e..e4c355eaf5185 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -587,6 +587,9 @@ defm CooperativeMatrixBFloat16ComponentTypeINTEL : CapabilityOperand<6437, 0, 0,
 defm RoundToInfinityINTEL : CapabilityOperand<5582, 0, 0, [SPV_INTEL_float_controls2], []>;
 defm FloatingPointModeINTEL : CapabilityOperand<5583, 0, 0, [SPV_INTEL_float_controls2], []>;
 defm FunctionFloatControlINTEL : CapabilityOperand<5821, 0, 0, [SPV_INTEL_float_controls2], []>;
+defm KernelAttributesINTEL : CapabilityOperand<5892, 0, 0, [SPV_INTEL_kernel_attributes], [Kernel]>;
+defm FPGAKernelAttributesINTEL : CapabilityOperand<5897, 0, 0, [SPV_INTEL_kernel_attributes], [Kernel]>;
+defm FPGAKernelAttributesv2INTEL : CapabilityOperand<6161, 0, 0, [SPV_INTEL_kernel_attributes], [Kernel]>;
 defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composites], []>;
 defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>;
 defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
@@ -805,6 +808,13 @@ defm RoundingModeRTPINTEL : ExecutionModeOperand<5620, [RoundToInfinityINTEL]>;
 defm RoundingModeRTNINTEL : ExecutionModeOperand<5621, [RoundToInfinityINTEL]>;
 defm FloatingPointModeALTINTEL : ExecutionModeOperand<5622, [FloatingPointModeINTEL]>;
 defm FloatingPointModeIEEEINTEL : ExecutionModeOperand<5623, [FloatingPointModeINTEL]>;
+defm MaxWorkgroupSizeINTEL : ExecutionModeOperand<5893, [KernelAttributesINTEL]>;
+defm MaxWorkDimINTEL : ExecutionModeOperand<5894, [KernelAttributesINTEL]>;
+defm NoGlobalOffsetINTEL : ExecutionModeOperand<5895, [KernelAttributesINTEL]>;
+defm NumSIMDWorkitemsINTEL : ExecutionModeOperand<5896, [FPGAKernelAttributesINTEL]>;
+defm SchedulerTargetFmaxMhzINTEL : ExecutionModeOperand<5903, [FPGAKernelAttributesINTEL]>;
+defm StreamingInterfaceINTEL : ExecutionModeOperand<6154, [FPGAKernelAttributesv2INTEL]>;
+defm RegisterMapInterfaceINTEL : ExecutionModeOperand<6160, [FPGAKernelAttributesv2INTEL]>;
 defm FPFastMathDefault : ExecutionModeOperand<6028, [FloatControls2]>;
 defm MaximallyReconvergesKHR : ExecutionModeOperand<6023, [Shader]>;
 
@@ -1919,7 +1929,7 @@ defm GenericCastToPtr :  SpecConstantOpOperandsOperand<122, [], [Kernel]>;
 defm PtrCastToGeneric :  SpecConstantOpOperandsOperand<121, [], [Kernel]>;
 defm Bitcast :  SpecConstantOpOperandsOperand<124, [], []>;
 defm QuantizeToF16 :  SpecConstantOpOperandsOperand<116, [], [Shader]>;
-// Arithmetic 
+// Arithmetic
 defm SNegate :  SpecConstantOpOperandsOperand<126, [], []>;
 defm Not :  SpecConstantOpOperandsOperand<200, [], []>;
 defm IAdd :  SpecConstantOpOperandsOperand<128, [], []>;
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_kernel_attributes/max_work_group_size.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_kernel_attributes/max_work_group_size.ll
new file mode 100644
index 0000000000000..717771c965496
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_kernel_attributes/max_work_group_size.ll
@@ -0,0 +1,32 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_kernel_attributes %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s
+; %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_kernel_attributes %s -o - -filetype=obj | spirv-val %}
+; %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpCapability KernelAttributesINTEL
+; CHECK: OpExtension "SPV_INTEL_kernel_attributes"
+; CHECK: OpEntryPoint {{.*}} %[[DIM1:[0-9]+]] "Dim1"
+; CHECK: OpEntryPoint {{.*}} %[[DIM2:[0-9]+]] "Dim2"
+; CHECK: OpEntryPoint {{.*}} %[[DIM3:[0-9]+]] "Dim3"
+; CHECK: OpExecutionMode %[[DIM1]] MaxWorkgroupSizeINTEL 4 1 1
+; CHECK: OpExecutionMode %[[DIM2]] MaxWorkgroupSizeINTEL 8 4 1
+; CHECK: OpExecutionMode %[[DIM3]] MaxWorkgroupSizeINTEL 16 8 4
+; CHECK: %[[DIM1]] = OpFunction
+; CHECK: %[[DIM2]] = OpFunction
+; CHECK: %[[DIM3]] = OpFunction
+
+define spir_kernel void @Dim1() !max_work_group_size !0 {
+  ret void
+}
+
+define spir_kernel void @Dim2() !max_work_group_size !1 {
+  ret void
+}
+
+define spir_kernel void @Dim3() !max_work_group_size !2 {
+  ret void
+}
+
+!0 = !{i32 4}
+!1 = !{i32 8, i32 4}
+!2 = !{i32 16, i32 8, i32 4}

…v_be_staging_1

github-actions · 2025-10-31T17:54:22Z

✅ With the latest revision this PR passed the C/C++ code formatter.

sarnex

lgtm but I'm not a SPV backend expert so please wait for one more review :)

MrSidims

Overall LGTM, I just would like to suggest to remove unused capabilities and decorations. Reason: non-empty grep on decorations' names might give a false impression, that they are implemented.
Also, what about:
Add SPV_INTEL_kernel_attributes ->
Enable OpenCL max_work_group_size translation via SPV_INTEL_kernel_attributes
?

llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td

AlexVlx

Overall LGTM, I just would like to suggest to remove unused capabilities and decorations. Reason: non-empty grep on decorations' names might give a false impression, that they are implemented.
Also, what about:
Add SPV_INTEL_kernel_attributes ->
Enable OpenCL max_work_group_size translation via SPV_INTEL_kernel_attributes
Done.
?

AlexVlx

Lets remove it for now

Done.

AlexVlx

Lets not add, what we are not using (better to leave a TODO).

Done.

AlexVlx added 13 commits May 15, 2025 23:27

Add pass which forwards unimplemented math builtins / libcalls to the…

3e0abe1

… HIPSTDPAR runtime component.

Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

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Merge branch 'main' of https://github.com/llvm/llvm-project

83dbc0d

Merge branch 'main' of https://github.com/llvm/llvm-project

4255cdd

Merge branch 'main' of https://github.com/llvm/llvm-project

de81a63

Add support for SPV_INTEL_kernel_attributes.

95f6005

AlexVlx added the backend:SPIR-V label Oct 31, 2025

AlexVlx requested review from MrSidims, VyacheslavLevytskyy, jmmartinez, mgcarrasco, michalpaszkowski and sarnex October 31, 2025 17:53

Merge branch 'main' of https://github.com/llvm/llvm-project into spir…

b219e29

…v_be_staging_1

AlexVlx added 3 commits October 31, 2025 19:55

Fix formatting.

f91b71f

Remove unrelated change.

7dcd767

Add relevant docs entry.

7777346

sarnex approved these changes Oct 31, 2025

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jmmartinez approved these changes Nov 3, 2025

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MrSidims reviewed Nov 3, 2025

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llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td Outdated Show resolved Hide resolved

llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td Outdated Show resolved Hide resolved

mgcarrasco approved these changes Nov 3, 2025

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AlexVlx changed the title ~~[SPIRV] Add SPV_INTEL_kernel_attributes~~ [SPIRV] Enable OpenCL max_work_group_size translation via SPV_INTEL_kernel_attributes Nov 3, 2025

AlexVlx commented Nov 3, 2025

View reviewed changes

Replace as of yet unimplemented bits with corresponding TODOs.

d2a9174

AlexVlx commented Nov 3, 2025

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MrSidims approved these changes Nov 3, 2025

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AlexVlx added 2 commits November 4, 2025 04:59

Merge branch 'main' into spirv_be_staging_1

a441ca6

Merge branch 'main' into spirv_be_staging_1

465b9cd

AlexVlx merged commit 2237a18 into llvm:main Nov 4, 2025
10 of 11 checks passed

AlexVlx deleted the spirv_be_staging_1 branch November 4, 2025 14:37

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[SPIRV] Enable OpenCL max_work_group_size translation via `SPV_INTEL_kernel_attributes` #165891

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