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[SelectionDAG][RISCV] Support STACK/PATCHPOINT in SoftenFloatOperand. #165922

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merged 2 commits into from
Nov 1, 2025
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[SelectionDAG][RISCV] Support STACK/PATCHPOINT in SoftenFloatOperand. #165922

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4b92f1e
[SelectionDAG][RISCV] Support STACK/PATCHPOINT in SoftenFloatOperand.
topperc Oct 31, 2025
45ba5fa
fixup! test half and bfloat too
topperc Oct 31, 2025
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20 changes: 20 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1172,6 +1172,12 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
case ISD::FAKE_USE:
Res = SoftenFloatOp_FAKE_USE(N);
break;
case ISD::STACKMAP:
Res = SoftenFloatOp_STACKMAP(N, OpNo);
break;
case ISD::PATCHPOINT:
Res = SoftenFloatOp_PATCHPOINT(N, OpNo);
break;
}

// If the result is null, the sub-method took care of registering results etc.
Expand Down Expand Up @@ -1512,6 +1518,20 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FAKE_USE(SDNode *N) {
N->getOperand(0), Op1);
}

SDValue DAGTypeLegalizer::SoftenFloatOp_STACKMAP(SDNode *N, unsigned OpNo) {
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
SmallVector<SDValue> NewOps(N->ops());
NewOps[OpNo] = GetSoftenedFloat(NewOps[OpNo]);
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
}

SDValue DAGTypeLegalizer::SoftenFloatOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
assert(OpNo >= 7);
SmallVector<SDValue> NewOps(N->ops());
NewOps[OpNo] = GetSoftenedFloat(NewOps[OpNo]);
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
}

//===----------------------------------------------------------------------===//
// Float Result Expansion
//===----------------------------------------------------------------------===//
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -658,6 +658,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatOp_ATOMIC_STORE(SDNode *N, unsigned OpNo);
SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
SDValue SoftenFloatOp_FAKE_USE(SDNode *N);
SDValue SoftenFloatOp_STACKMAP(SDNode *N, unsigned OpNo);
SDValue SoftenFloatOp_PATCHPOINT(SDNode *N, unsigned OpNo);

//===--------------------------------------------------------------------===//
// Float Expansion Support: LegalizeFloatTypes.cpp
Expand Down
108 changes: 105 additions & 3 deletions llvm/test/CodeGen/RISCV/rv64-stackmap.ll
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Expand Up @@ -7,11 +7,11 @@
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 0
; Num Functions
; CHECK-NEXT: .word 12
; CHECK-NEXT: .word 13
; Num LargeConstants
; CHECK-NEXT: .word 2
; CHECK-NEXT: .word 3
; Num Callsites
; CHECK-NEXT: .word 16
; CHECK-NEXT: .word 17

; Functions and stack size
; CHECK-NEXT: .quad constantargs
Expand Down Expand Up @@ -50,10 +50,14 @@
; CHECK-NEXT: .quad needsStackRealignment
; CHECK-NEXT: .quad -1
; CHECK-NEXT: .quad 1
; CHECK-NEXT: .quad floats
; CHECK-NEXT: .quad 32
; CHECK-NEXT: .quad 1

; Num LargeConstants
; CHECK-NEXT: .quad 4294967295
; CHECK-NEXT: .quad 4294967296
; CHECK-NEXT: .quad 4609434218613702656

; Constant arguments
;
Expand Down Expand Up @@ -379,6 +383,104 @@ define void @needsStackRealignment() {
}
declare void @escape_values(...)

; CHECK-LABEL: .word .L{{.*}}-floats
; CHECK-NEXT: .half 0
; Num Locations
; CHECK-NEXT: .half 12
; Loc 0: constant float as constant integer
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 0
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 1: constant double as large constant integer
; CHECK-NEXT: .byte 5
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 0
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 2: constant half as constant integer
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 0
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 3: constant bfloat as constant integer
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 0
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 4: float value in X register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 10
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 5: double value in X register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 11
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 6: half value in X register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 12
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 7: bfloat value in X register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 13
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 8: float on stack
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 2
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 9: double on stack
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 2
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 10: half on stack
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 2
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
; Loc 11: bfloat on stack
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .half 8
; CHECK-NEXT: .half 2
; CHECK-NEXT: .half 0
; CHECK-NEXT: .word
define void @floats(float %f, double %g, half %h, bfloat %i) {
%ff = alloca float
%gg = alloca double
%hh = alloca half
%ii = alloca bfloat
call void (i64, i32, ...) @llvm.experimental.stackmap(i64 888, i32 0, float 1.25,
double 1.5, half 1.5, bfloat 1.5, float %f, double %g, half %h, bfloat %i, ptr %ff, ptr %gg, ptr %hh, ptr %ii)
ret void
}

declare void @llvm.experimental.stackmap(i64, i32, ...)
declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)