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CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions #166213

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merged 1 commit into from
Nov 12, 2025
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CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions #166213

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56 changes: 33 additions & 23 deletions llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -794,29 +794,36 @@ bool TwoAddressInstructionImpl::convertInstTo3Addr(
if (!NewMI)
return false;

LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);

// If the old instruction is debug value tracked, an update is required.
if (auto OldInstrNum = mi->peekDebugInstrNum()) {
assert(mi->getNumExplicitDefs() == 1);
assert(NewMI->getNumExplicitDefs() == 1);

// Find the old and new def location.
unsigned OldIdx = mi->defs().begin()->getOperandNo();
unsigned NewIdx = NewMI->defs().begin()->getOperandNo();

// Record that one def has been replaced by the other.
unsigned NewInstrNum = NewMI->getDebugInstrNum();
MF->makeDebugValueSubstitution(std::make_pair(OldInstrNum, OldIdx),
std::make_pair(NewInstrNum, NewIdx));
}

MBB->erase(mi); // Nuke the old inst.

for (MachineInstr &MI : MIS)
DistanceMap.insert(std::make_pair(&MI, Dist++));
Dist--;

if (&*mi == NewMI) {
LLVM_DEBUG(dbgs() << "2addr: CONVERTED IN-PLACE TO 3-ADDR: " << *mi);
} else {
LLVM_DEBUG({
dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi;
dbgs() << "2addr: TO 3-ADDR: " << *NewMI;
});

// If the old instruction is debug value tracked, an update is required.
if (auto OldInstrNum = mi->peekDebugInstrNum()) {
assert(mi->getNumExplicitDefs() == 1);
assert(NewMI->getNumExplicitDefs() == 1);

// Find the old and new def location.
unsigned OldIdx = mi->defs().begin()->getOperandNo();
unsigned NewIdx = NewMI->defs().begin()->getOperandNo();

// Record that one def has been replaced by the other.
unsigned NewInstrNum = NewMI->getDebugInstrNum();
MF->makeDebugValueSubstitution(std::make_pair(OldInstrNum, OldIdx),
std::make_pair(NewInstrNum, NewIdx));
}

MBB->erase(mi); // Nuke the old inst.
Dist--;
}

mi = NewMI;
nmi = std::next(mi);

Expand Down Expand Up @@ -1329,6 +1336,9 @@ bool TwoAddressInstructionImpl::tryInstructionTransform(

bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);

// Give targets a chance to convert bundled instructions.
bool ConvertibleTo3Addr = MI.isConvertibleTo3Addr(MachineInstr::AnyInBundle);

// If the instruction is convertible to 3 Addr, instead
// of returning try 3 Addr transformation aggressively and
// use this variable to check later. Because it might be better.
Expand All @@ -1337,7 +1347,7 @@ bool TwoAddressInstructionImpl::tryInstructionTransform(
// addl %esi, %edi
// movl %edi, %eax
// ret
if (Commuted && !MI.isConvertibleTo3Addr())
if (Commuted && !ConvertibleTo3Addr)
return false;

if (shouldOnlyCommute)
Expand All @@ -1357,7 +1367,7 @@ bool TwoAddressInstructionImpl::tryInstructionTransform(
regBKilled = isKilled(MI, regB, true);
}

if (MI.isConvertibleTo3Addr()) {
if (ConvertibleTo3Addr) {
// This instruction is potentially convertible to a true
// three-address instruction. Check if it is profitable.
if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
Expand Down
57 changes: 53 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -4046,10 +4046,29 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
LiveVariables *LV,
LiveIntervals *LIS) const {
MachineBasicBlock &MBB = *MI.getParent();
MachineInstr *CandidateMI = &MI;

if (MI.isBundle()) {
// This is a temporary placeholder for bundle handling that enables us to
// exercise the relevant code paths in the two-address instruction pass.
if (MI.getBundleSize() != 1)
return nullptr;
CandidateMI = MI.getNextNode();
}

ThreeAddressUpdates U;
MachineInstr *NewMI = convertToThreeAddressImpl(MI, U);
MachineInstr *NewMI = convertToThreeAddressImpl(*CandidateMI, U);
if (!NewMI)
return nullptr;

if (NewMI) {
if (MI.isBundle()) {
CandidateMI->eraseFromBundle();

for (MachineOperand &MO : MI.all_defs()) {
if (MO.isTied())
MI.untieRegOperand(MO.getOperandNo());
}
} else {
updateLiveVariables(LV, MI, *NewMI);
if (LIS) {
LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
Expand Down Expand Up @@ -4090,7 +4109,22 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
LV->getVarInfo(DefReg).AliveBlocks.clear();
}

if (LIS) {
if (MI.isBundle()) {
VirtRegInfo VRI = AnalyzeVirtRegInBundle(MI, DefReg);
if (!VRI.Reads && !VRI.Writes) {
for (MachineOperand &MO : MI.all_uses()) {
if (MO.isReg() && MO.getReg() == DefReg) {
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@arsenm arsenm Nov 5, 2025

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Test case with subregister operand?

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@nhaehnle nhaehnle Nov 6, 2025

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See the discussion with Jay in #166212 -- I looked into it and decided to just prevent and forbid tied sub-registers on bundles in pre-RA as the safer route due to the complexities involved.

I'm adding an assert to that effect here.

assert(MO.getSubReg() == 0 &&
"tied sub-registers in bundles currently not supported");
MI.removeOperand(MO.getOperandNo());
break;
}
}

if (LIS)
LIS->shrinkToUses(&LIS->getInterval(DefReg));
}
} else if (LIS) {
LiveInterval &DefLI = LIS->getInterval(DefReg);

// We cannot delete the original instruction here, so hack out the use
Expand All @@ -4105,11 +4139,26 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
}

if (MI.isBundle()) {
VirtRegInfo VRI = AnalyzeVirtRegInBundle(MI, DefReg);
if (!VRI.Reads && !VRI.Writes) {
for (MachineOperand &MIOp : MI.uses()) {
if (MIOp.isReg() && MIOp.getReg() == DefReg) {
MIOp.setIsUndef(true);
MIOp.setReg(DummyReg);
}
}
}

MI.addOperand(MachineOperand::CreateReg(DummyReg, false, false, false,
false, /*isUndef=*/true));
}

LIS->shrinkToUses(&DefLI);
}
}

return NewMI;
return MI.isBundle() ? &MI : NewMI;
}

MachineInstr *
Expand Down
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/AMDGPU/twoaddr-bundle.mir
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Expand Up @@ -31,7 +31,7 @@ body: |

...

# This test is an example where conversion to three-address form would be beneficial.
# This test is an example where conversion to three-address form is beneficial.
---
name: test_fmac_reuse_bundle
body: |
Expand All @@ -41,11 +41,10 @@ body: |
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN-NEXT: BUNDLE implicit-def [[COPY1]], implicit [[DEF]], implicit [[DEF1]], implicit [[COPY1]](tied-def 0), implicit $mode, implicit $exec {
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e32 killed [[DEF]], killed [[DEF1]], killed [[COPY1]], implicit $mode, implicit $exec
; GCN-NEXT: BUNDLE implicit-def %3, implicit [[DEF]], implicit [[DEF1]], implicit [[COPY]], implicit $mode, implicit $exec {
; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, killed [[DEF]], 0, killed [[DEF1]], 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: }
; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY1]], [[COPY]], 0, implicit $exec
; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_FMA_F32_e64_]], [[COPY]], 0, implicit $exec
%2:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
Expand Down
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