Skip to content

[AArch64][SME] Add support for zeroing ZT0 to CommitZASavePseudo #166360

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
MacDue merged 1 commit into from
Nov 18, 2025
Merged

[AArch64][SME] Add support for zeroing ZT0 to CommitZASavePseudo #166360

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 9 additions & 4 deletions llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1063,6 +1063,7 @@ AArch64ExpandPseudo::expandCommitZASave(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
[[maybe_unused]] auto *RI = MBB.getParent()->getSubtarget().getRegisterInfo();

// Compare TPIDR2_EL0 against 0. Commit ZA if TPIDR2_EL0 is non-zero.
MachineInstrBuilder Branch =
Expand All @@ -1073,21 +1074,25 @@ AArch64ExpandPseudo::expandCommitZASave(MachineBasicBlock &MBB,
MachineInstrBuilder MIB =
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::BL));
// Copy operands (mainly the regmask) from the pseudo.
for (unsigned I = 2; I < MI.getNumOperands(); ++I)
for (unsigned I = 3; I < MI.getNumOperands(); ++I)
MIB.add(MI.getOperand(I));
// Clear TPIDR2_EL0.
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::MSR))
.addImm(AArch64SysReg::TPIDR2_EL0)
.addReg(AArch64::XZR);
bool ZeroZA = MI.getOperand(1).getImm() != 0;
bool ZeroZT0 = MI.getOperand(2).getImm() != 0;
if (ZeroZA) {
[[maybe_unused]] auto *TRI =
MBB.getParent()->getSubtarget().getRegisterInfo();
assert(MI.definesRegister(AArch64::ZAB0, TRI) && "should define ZA!");
assert(MI.definesRegister(AArch64::ZAB0, RI) && "should define ZA!");
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::ZERO_M))
.addImm(ZERO_ALL_ZA_MASK)
.addDef(AArch64::ZAB0, RegState::ImplicitDefine);
}
if (ZeroZT0) {
assert(MI.definesRegister(AArch64::ZT0, RI) && "should define ZT0!");
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::ZERO_T))
.addDef(AArch64::ZT0);
}

MI.eraseFromParent();
return &EndBB;
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,8 @@ def SMEStateAllocPseudo : Pseudo<(outs), (ins), []>, Sched<[]>;

def CommitZASavePseudo
: Pseudo<(outs),
(ins GPR64:$tpidr2_el0, i1imm:$zero_za, i64imm:$commit_routine, variable_ops), []>,
(ins GPR64:$tpidr2_el0, i1imm:$zero_za, i1imm:$zero_zt0,
i64imm:$commit_routine, variable_ops), []>,
Sched<[]>;

def AArch64_inout_za_use
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -842,6 +842,7 @@ void MachineSMEABI::emitNewZAPrologue(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, DL, TII->get(AArch64::CommitZASavePseudo))
.addReg(TPIDR2EL0)
.addImm(ZeroZA ? 1 : 0)
.addImm(/*ZeroZT0=*/false)
.addExternalSymbol(TLI->getLibcallName(RTLIB::SMEABI_TPIDR2_SAVE))
.addRegMask(TRI->SMEABISupportRoutinesCallPreservedMaskFromX0());
if (ZeroZA)
Expand Down
69 changes: 67 additions & 2 deletions llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ body: |
; CHECK-NEXT: RET undef $lr
$x8 = MRS 56965, implicit-def $nzcv

CommitZASavePseudo $x8, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
CommitZASavePseudo $x8, 0, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0

RET_ReallyLR

Expand Down Expand Up @@ -94,7 +94,72 @@ body: |
; CHECK-NEXT: RET undef $lr
$x8 = MRS 56965, implicit-def $nzcv

CommitZASavePseudo $x8, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0
CommitZASavePseudo $x8, 1, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0

RET_ReallyLR

...
---
# X8 = TPIDR2_EL0
name: commit_za_save_zero_zt0
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: commit_za_save_zero_zt0
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x8 = MRS 56965, implicit-def $nzcv
; CHECK-NEXT: CBNZX $x8, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: .1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zt0
; CHECK-NEXT: MSR 56965, $xzr
; CHECK-NEXT: $zt0 = ZERO_T
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: .2:
; CHECK-NEXT: RET undef $lr
$x8 = MRS 56965, implicit-def $nzcv

CommitZASavePseudo $x8, 0, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zt0

RET_ReallyLR

...
---
# X8 = TPIDR2_EL0
name: commit_za_save_zero_everything
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: commit_za_save_zero_everything
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x8 = MRS 56965, implicit-def $nzcv
; CHECK-NEXT: CBNZX $x8, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: .1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zab0, implicit-def $zt0
; CHECK-NEXT: MSR 56965, $xzr
; CHECK-NEXT: ZERO_M 255, implicit-def $zab0
; CHECK-NEXT: $zt0 = ZERO_T
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: .2:
; CHECK-NEXT: RET undef $lr
$x8 = MRS 56965, implicit-def $nzcv

CommitZASavePseudo $x8, 1, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0, implicit-def $zt0

RET_ReallyLR

Expand Down
Loading