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[llvm][RISCV] Do not assume V extension on seeing vector type. #166994

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Merged
merged 2 commits into from
Nov 7, 2025
Merged

[llvm][RISCV] Do not assume V extension on seeing vector type. #166994

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a46983a
[llvm][RISCV] Do not assume V extension on seeing vector type.
wecing Nov 7, 2025
b7abc70
use ST->hasVInstructions() and reduce if-nesting
wecing Nov 7, 2025
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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2140,8 +2140,9 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
// Assume memory ops cost scale with the number of vector registers
// possible accessed by the instruction. Note that BasicTTI already
// handles the LT.first term for us.
if (LT.second.isVector() && CostKind != TTI::TCK_CodeSize)
BaseCost *= TLI->getLMULCost(LT.second);
if (TLI->getSubtarget().hasVInstructions())
if (LT.second.isVector() && CostKind != TTI::TCK_CodeSize)
BaseCost *= TLI->getLMULCost(LT.second);
return Cost + BaseCost;
}

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