[AMDGPU] [DO NOT MERGE] Nonsuccessful Attempt At Using SelectionDAG Hooks for abs i8/i16 #167064
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…rom this approach.
You can test this locally with the following command:git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h --diff_from_common_commit
View the diff from clang-format here.diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 95910b68f..de6394b76 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -181,7 +181,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// We don't want the default expansion of 16-bit ABS since we can
// sign-extend and use the 32-bit ABS operation for 16-bit ABS with SGPRs
- setOperationAction(ISD::ABS, {MVT::i8,MVT::i16}, Custom);
+ setOperationAction(ISD::ABS, {MVT::i8, MVT::i16}, Custom);
}
addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
@@ -7281,7 +7281,7 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
void SITargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
- switch (N->getOpcode()) {
+ switch (N->getOpcode()) {
case ISD::INSERT_VECTOR_ELT: {
if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
Results.push_back(Res);
@@ -7462,7 +7462,7 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::ABS:
if (N->getValueType(0) == MVT::i16 || N->getValueType(0) == MVT::i8) {
SDValue result = lowerABSi16(SDValue(N, 0), DAG);
- if(result!=SDValue()) {
+ if (result != SDValue()) {
Results.push_back(result);
return;
}
@@ -16894,7 +16894,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
switch (N->getOpcode()) {
case ISD::ABS:
if (N->getValueType(0) == MVT::i16 || N->getValueType(0) == MVT::i8)
- return lowerABSi16(SDValue(N,0), DCI.DAG);
+ return lowerABSi16(SDValue(N, 0), DCI.DAG);
break;
case ISD::ADD:
return performAddCombine(N, DCI);
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arsenm
reviewed
Nov 8, 2025
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| // We don't want the default expansion of 16-bit ABS since we can | ||
| // sign-extend and use the 32-bit ABS operation for 16-bit ABS with SGPRs | ||
| setOperationAction(ISD::ABS, {MVT::i8,MVT::i16}, Custom); |
Contributor
There was a problem hiding this comment.
It will be easier to ignore i8 for now and just get i16 working. i8 adds way more problems if you're having trouble with the easy case
| @@ -7450,6 +7459,15 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N, | |||
| Results.push_back(lowerFSQRTF16(SDValue(N, 0), DAG)); | |||
| break; | |||
| } | |||
| case ISD::ABS: | |||
| if (N->getValueType(0) == MVT::i16 || N->getValueType(0) == MVT::i8) { | |||
Contributor
There was a problem hiding this comment.
i16 won't reach here in the relevant case. It would happen for <= gfx7
| assert((Op.getValueType() == MVT::i16 || Op.getValueType() == MVT::i8) && | ||
| "Tried to select abs i16 lowering with non-i16 type."); | ||
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| // divergent means will not end up using SGPRs |
Contributor
There was a problem hiding this comment.
This is stronger of an assertion than is true, it's just more likely
| if (Op->isDivergent()) | ||
| return SDValue(); | ||
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| //(abs i16 (i16 op1)) -> (trunc i16 (abs i32 (sext i32 (i16 op1)))) |
Contributor
There was a problem hiding this comment.
Suggested change
| //(abs i16 (i16 op1)) -> (trunc i16 (abs i32 (sext i32 (i16 op1)))) | |
| // (abs i16 (i16 op1)) -> (trunc i16 (abs i32 (sext i32 (i16 op1)))) |
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| // divergent means will not end up using SGPRs | ||
| if (Op->isDivergent()) | ||
| return SDValue(); |
Contributor
There was a problem hiding this comment.
This is the opposite of what you want:
Suggested change
| return SDValue(); | |
| return Op; |
To get the default expansion, you return the original node. Return SDValue() means treat as legal
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This is to demonstrate that setOperationAction does not work to solve SWDEV-562122. See #165626