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[VE] Use MCRegister instead of unsigned. NFC #167460

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Merged
merged 4 commits into from
Nov 11, 2025
Merged

[VE] Use MCRegister instead of unsigned. NFC #167460

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33b4f71
[VE] Use MCRegister instead of unsigned. NFC
topperc Nov 11, 2025
00d1492
fixup! clang-format
topperc Nov 11, 2025
cf05d46
fixup! missed a spot
topperc Nov 11, 2025
e7ab8bd
fixup! RegNum->Reg
topperc Nov 11, 2025
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76 changes: 39 additions & 37 deletions llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ class VEAsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
int parseRegisterName(MCRegister (*matchFn)(StringRef));
MCRegister parseRegisterName(MCRegister (*matchFn)(StringRef));
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
Expand Down Expand Up @@ -169,16 +169,16 @@ class VEOperand : public MCParsedAsmOperand {
};

struct RegOp {
unsigned RegNum;
MCRegister Reg;
};

struct ImmOp {
const MCExpr *Val;
};

struct MemOp {
unsigned Base;
unsigned IndexReg;
MCRegister Base;
MCRegister IndexReg;
const MCExpr *Index;
const MCExpr *Offset;
};
Expand Down Expand Up @@ -342,22 +342,22 @@ class VEOperand : public MCParsedAsmOperand {

MCRegister getReg() const override {
assert((Kind == k_Register) && "Invalid access!");
return Reg.RegNum;
return Reg.Reg;
}

const MCExpr *getImm() const {
assert((Kind == k_Immediate) && "Invalid access!");
return Imm.Val;
}

unsigned getMemBase() const {
MCRegister getMemBase() const {
assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
Kind == k_MemoryRegImm) &&
"Invalid access!");
return Mem.Base;
}

unsigned getMemIndexReg() const {
MCRegister getMemIndexReg() const {
assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm) &&
"Invalid access!");
return Mem.IndexReg;
Expand Down Expand Up @@ -415,28 +415,29 @@ class VEOperand : public MCParsedAsmOperand {
OS << "Token: " << getToken() << "\n";
break;
case k_Register:
OS << "Reg: #" << getReg() << "\n";
OS << "Reg: #" << getReg().id() << "\n";
break;
case k_Immediate:
OS << "Imm: " << getImm() << "\n";
break;
case k_MemoryRegRegImm:
assert(getMemOffset() != nullptr);
OS << "Mem: #" << getMemBase() << "+#" << getMemIndexReg() << "+";
OS << "Mem: #" << getMemBase().id() << "+#" << getMemIndexReg().id()
<< "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
case k_MemoryRegImmImm:
assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
OS << "Mem: #" << getMemBase() << "+";
OS << "Mem: #" << getMemBase().id() << "+";
MAI.printExpr(OS, *getMemIndex());
OS << "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
case k_MemoryZeroRegImm:
assert(getMemOffset() != nullptr);
OS << "Mem: 0+#" << getMemIndexReg() << "+";
OS << "Mem: 0+#" << getMemIndexReg().id() << "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
Expand All @@ -450,7 +451,7 @@ class VEOperand : public MCParsedAsmOperand {
break;
case k_MemoryRegImm:
assert(getMemOffset() != nullptr);
OS << "Mem: #" << getMemBase() << "+";
OS << "Mem: #" << getMemBase().id() << "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
Expand Down Expand Up @@ -606,10 +607,10 @@ class VEOperand : public MCParsedAsmOperand {
return Op;
}

static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S,
static std::unique_ptr<VEOperand> CreateReg(MCRegister Reg, SMLoc S,
SMLoc E) {
auto Op = std::make_unique<VEOperand>(k_Register);
Op->Reg.RegNum = RegNum;
Op->Reg.Reg = Reg;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
Expand Down Expand Up @@ -653,38 +654,38 @@ class VEOperand : public MCParsedAsmOperand {
}

static bool MorphToI32Reg(VEOperand &Op) {
unsigned Reg = Op.getReg();
MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx > 63)
return false;
Op.Reg.RegNum = I32Regs[regIdx];
Op.Reg.Reg = I32Regs[regIdx];
return true;
}

static bool MorphToF32Reg(VEOperand &Op) {
unsigned Reg = Op.getReg();
MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx > 63)
return false;
Op.Reg.RegNum = F32Regs[regIdx];
Op.Reg.Reg = F32Regs[regIdx];
return true;
}

static bool MorphToF128Reg(VEOperand &Op) {
unsigned Reg = Op.getReg();
MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx % 2 || regIdx > 63)
return false;
Op.Reg.RegNum = F128Regs[regIdx / 2];
Op.Reg.Reg = F128Regs[regIdx / 2];
return true;
}

static bool MorphToVM512Reg(VEOperand &Op) {
unsigned Reg = Op.getReg();
MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::VM0;
if (regIdx % 2 || regIdx > 15)
return false;
Op.Reg.RegNum = VM512Regs[regIdx / 2];
Op.Reg.Reg = VM512Regs[regIdx / 2];
return true;
}

Expand All @@ -696,16 +697,16 @@ class VEOperand : public MCParsedAsmOperand {
if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
return false;
Op.Kind = k_Register;
Op.Reg.RegNum = MISCRegs[regIdx];
Op.Reg.Reg = MISCRegs[regIdx];
return true;
}

static std::unique_ptr<VEOperand>
MorphToMEMri(unsigned Base, std::unique_ptr<VEOperand> Op) {
MorphToMEMri(MCRegister Base, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryRegImm;
Op->Mem.Base = Base;
Op->Mem.IndexReg = 0;
Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = nullptr;
Op->Mem.Offset = Imm;
return Op;
Expand All @@ -715,15 +716,16 @@ class VEOperand : public MCParsedAsmOperand {
MorphToMEMzi(std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryZeroImm;
Op->Mem.Base = 0;
Op->Mem.IndexReg = 0;
Op->Mem.Base = MCRegister();
Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = nullptr;
Op->Mem.Offset = Imm;
return Op;
}

static std::unique_ptr<VEOperand>
MorphToMEMrri(unsigned Base, unsigned Index, std::unique_ptr<VEOperand> Op) {
MorphToMEMrri(MCRegister Base, MCRegister Index,
std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryRegRegImm;
Op->Mem.Base = Base;
Expand All @@ -734,22 +736,22 @@ class VEOperand : public MCParsedAsmOperand {
}

static std::unique_ptr<VEOperand>
MorphToMEMrii(unsigned Base, const MCExpr *Index,
MorphToMEMrii(MCRegister Base, const MCExpr *Index,
std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryRegImmImm;
Op->Mem.Base = Base;
Op->Mem.IndexReg = 0;
Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = Index;
Op->Mem.Offset = Imm;
return Op;
}

static std::unique_ptr<VEOperand>
MorphToMEMzri(unsigned Index, std::unique_ptr<VEOperand> Op) {
MorphToMEMzri(MCRegister Index, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryZeroRegImm;
Op->Mem.Base = 0;
Op->Mem.Base = MCRegister();
Op->Mem.IndexReg = Index;
Op->Mem.Index = nullptr;
Op->Mem.Offset = Imm;
Expand All @@ -760,8 +762,8 @@ class VEOperand : public MCParsedAsmOperand {
MorphToMEMzii(const MCExpr *Index, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryZeroImmImm;
Op->Mem.Base = 0;
Op->Mem.IndexReg = 0;
Op->Mem.Base = MCRegister();
Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = Index;
Op->Mem.Offset = Imm;
return Op;
Expand Down Expand Up @@ -815,14 +817,14 @@ bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,

/// Parses a register name using a given matching function.
/// Checks for lowercase or uppercase if necessary.
int VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
MCRegister VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
StringRef Name = Parser.getTok().getString();

int RegNum = matchFn(Name);
MCRegister RegNum = matchFn(Name);

// GCC supports case insensitive register names. All of the VE registers
// are all lower case.
if (RegNum == VE::NoRegister) {
if (!RegNum) {
RegNum = matchFn(Name.lower());
}

Expand Down
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