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[lldb][RISCV] Fix float load and stores in RISC-V emulator #167490

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Merged
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Nov 11, 2025
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[lldb][RISCV] Fix float load and stores in RISC-V emulator #167490

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30 changes: 18 additions & 12 deletions lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1328,32 +1328,36 @@ class Executor {
m_emu, inst, 8, ZextD,
[](uint64_t a, uint64_t b) { return std::max(a, b); });
}
template <typename T>
bool F_Load(T inst, const fltSemantics &(*semantics)(),
unsigned int numBits) {
template <typename I, typename T>
bool F_Load(I inst, const fltSemantics &(*semantics)()) {
return transformOptional(inst.rs1.Read(m_emu),
[&](auto &&rs1) {
uint64_t addr = rs1 + uint64_t(inst.imm);
uint64_t bits = *m_emu.ReadMem<uint64_t>(addr);
uint64_t addr =
rs1 + uint64_t(SignExt(inst.imm));
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@lenary lenary Nov 11, 2025

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Is this the right width of sign extension?

The function only seems to cast from a uint32_t to an int32_t, which iirc will sign extend from the 32nd bit, not the 12th bit? Nowhere between decode and emulation do I see something specifically calling out 12, but I'm not familiar with LLDB, so I might have missed somewhere.

I'm not even sure that LoadStoreAddr(EmulateInstructionRISCV &emulator, I inst) is correct either.

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@DavidSpickett DavidSpickett Nov 17, 2025

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ping @sga-sc

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@DavidSpickett DavidSpickett Nov 17, 2025

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There is SignExtend32 in llvm/include/llvm/Support/MathExtras.h that could handle this.

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@sga-sc sga-sc Nov 17, 2025

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Should I create a new PR which fixes sign extention here and in LoadStoreAddr(EmulateInstructionRISCV &emulator, I inst)?

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@DavidSpickett DavidSpickett Nov 17, 2025 •
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Assuming you agree that this is an issue, yes please. From this snippet, it does seem incorrect but I haven't looked at the supporting code myself.

uint64_t bits = *m_emu.ReadMem<T>(addr);
unsigned numBits = sizeof(T) * 8;
APFloat f(semantics(), APInt(numBits, bits));
return inst.rd.WriteAPFloat(m_emu, f);
})
.value_or(false);
}
bool operator()(FLW inst) { return F_Load(inst, &APFloat::IEEEsingle, 32); }
template <typename T> bool F_Store(T inst, bool isDouble) {
bool operator()(FLW inst) {
return F_Load<FLW, uint32_t>(inst, &APFloat::IEEEsingle);
}
template <typename I, typename T> bool F_Store(I inst, bool isDouble) {
return transformOptional(zipOpt(inst.rs1.Read(m_emu),
inst.rs2.ReadAPFloat(m_emu, isDouble)),
[&](auto &&tup) {
auto [rs1, rs2] = tup;
uint64_t addr = rs1 + uint64_t(inst.imm);
uint64_t addr =
rs1 + uint64_t(SignExt(inst.imm));
uint64_t bits =
rs2.bitcastToAPInt().getZExtValue();
return m_emu.WriteMem<uint64_t>(addr, bits);
return m_emu.WriteMem<T>(addr, bits);
})
.value_or(false);
}
bool operator()(FSW inst) { return F_Store(inst, false); }
bool operator()(FSW inst) { return F_Store<FSW, uint32_t>(inst, false); }
std::tuple<bool, APFloat> FusedMultiplyAdd(APFloat rs1, APFloat rs2,
APFloat rs3) {
auto opStatus = rs1.fusedMultiplyAdd(rs2, rs3, m_emu.GetRoundingMode());
Expand Down Expand Up @@ -1616,8 +1620,10 @@ class Executor {
bool operator()(FCVT_S_LU inst) {
return FCVT_f2i(inst, &Rs::Read, APFloat::IEEEsingle());
}
bool operator()(FLD inst) { return F_Load(inst, &APFloat::IEEEdouble, 64); }
bool operator()(FSD inst) { return F_Store(inst, true); }
bool operator()(FLD inst) {
return F_Load<FLD, uint64_t>(inst, &APFloat::IEEEdouble);
}
bool operator()(FSD inst) { return F_Store<FSD, uint64_t>(inst, true); }
bool operator()(FMADD_D inst) { return FMA(inst, true, 1.0f, 1.0f); }
bool operator()(FMSUB_D inst) { return FMA(inst, true, 1.0f, -1.0f); }
bool operator()(FNMSUB_D inst) { return FMA(inst, true, -1.0f, 1.0f); }
Expand Down
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