[AArch64] Use MCRegister instead of unsigned. NFC #167547
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@llvm/pr-subscribers-backend-aarch64 Author: Craig Topper (topperc) ChangesFull diff: https://github.com/llvm/llvm-project/pull/167547.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 6273cfc1005d6..74221e424a4a0 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -88,7 +88,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
StringRef Mnemonic; ///< Instruction mnemonic.
// Map of register aliases registers via the .req directive.
- StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
+ StringMap<std::pair<RegKind, MCRegister>> RegisterReqs;
class PrefixInfo {
public:
@@ -165,7 +165,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
AArch64CC::CondCode parseCondCodeString(StringRef Cond,
std::string &Suggestion);
bool parseCondCode(OperandVector &Operands, bool invertCondCode);
- unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
+ MCRegister matchRegisterNameAlias(StringRef Name, RegKind Kind);
bool parseRegister(OperandVector &Operands);
bool parseSymbolicImmVal(const MCExpr *&ImmVal);
bool parseNeonVectorList(OperandVector &Operands);
@@ -391,7 +391,7 @@ class AArch64Operand : public MCParsedAsmOperand {
};
struct RegOp {
- unsigned RegNum;
+ MCRegister Reg;
RegKind Kind;
int ElementWidth;
@@ -417,7 +417,7 @@ class AArch64Operand : public MCParsedAsmOperand {
};
struct MatrixRegOp {
- unsigned RegNum;
+ MCRegister Reg;
unsigned ElementWidth;
MatrixKind Kind;
};
@@ -427,7 +427,7 @@ class AArch64Operand : public MCParsedAsmOperand {
};
struct VectorListOp {
- unsigned RegNum;
+ MCRegister Reg;
unsigned Count;
unsigned Stride;
unsigned NumElements;
@@ -688,12 +688,12 @@ class AArch64Operand : public MCParsedAsmOperand {
MCRegister getReg() const override {
assert(Kind == k_Register && "Invalid access!");
- return Reg.RegNum;
+ return Reg.Reg;
}
unsigned getMatrixReg() const {
assert(Kind == k_MatrixRegister && "Invalid access!");
- return MatrixReg.RegNum;
+ return MatrixReg.Reg;
}
unsigned getMatrixElementWidth() const {
@@ -718,7 +718,7 @@ class AArch64Operand : public MCParsedAsmOperand {
unsigned getVectorListStart() const {
assert(Kind == k_VectorList && "Invalid access!");
- return VectorList.RegNum;
+ return VectorList.Reg;
}
unsigned getVectorListCount() const {
@@ -1264,15 +1264,15 @@ class AArch64Operand : public MCParsedAsmOperand {
bool isNeonVectorRegLo() const {
return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
(AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains(
- Reg.RegNum) ||
+ Reg.Reg) ||
AArch64MCRegisterClasses[AArch64::FPR64_loRegClassID].contains(
- Reg.RegNum));
+ Reg.Reg));
}
bool isNeonVectorReg0to7() const {
return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
(AArch64MCRegisterClasses[AArch64::FPR128_0to7RegClassID].contains(
- Reg.RegNum));
+ Reg.Reg));
}
bool isMatrix() const { return Kind == k_MatrixRegister; }
@@ -1401,34 +1401,34 @@ class AArch64Operand : public MCParsedAsmOperand {
bool isGPR32as64() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
+ AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.Reg);
}
bool isGPR64as32() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
+ AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.Reg);
}
bool isGPR64x8() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].contains(
- Reg.RegNum);
+ Reg.Reg);
}
bool isWSeqPair() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
- Reg.RegNum);
+ Reg.Reg);
}
bool isXSeqPair() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
- Reg.RegNum);
+ Reg.Reg);
}
bool isSyspXzrPair() const {
- return isGPR64<AArch64::GPR64RegClassID>() && Reg.RegNum == AArch64::XZR;
+ return isGPR64<AArch64::GPR64RegClassID>() && Reg.Reg == AArch64::XZR;
}
template<int64_t Angle, int64_t Remainder>
@@ -1495,7 +1495,7 @@ class AArch64Operand : public MCParsedAsmOperand {
isTypedVectorList<VectorKind, NumRegs, NumElements, ElementWidth>();
if (!Res)
return DiagnosticPredicate::NoMatch;
- if (!AArch64MCRegisterClasses[RegClass].contains(VectorList.RegNum))
+ if (!AArch64MCRegisterClasses[RegClass].contains(VectorList.Reg))
return DiagnosticPredicate::NearMatch;
return DiagnosticPredicate::Match;
}
@@ -1507,9 +1507,9 @@ class AArch64Operand : public MCParsedAsmOperand {
ElementWidth, Stride>();
if (!Res)
return DiagnosticPredicate::NoMatch;
- if ((VectorList.RegNum < (AArch64::Z0 + Stride)) ||
- ((VectorList.RegNum >= AArch64::Z16) &&
- (VectorList.RegNum < (AArch64::Z16 + Stride))))
+ if ((VectorList.Reg < (AArch64::Z0 + Stride)) ||
+ ((VectorList.Reg >= AArch64::Z16) &&
+ (VectorList.Reg < (AArch64::Z16 + Stride))))
return DiagnosticPredicate::Match;
return DiagnosticPredicate::NoMatch;
}
@@ -1841,7 +1841,7 @@ class AArch64Operand : public MCParsedAsmOperand {
void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- unsigned Reg = getReg();
+ MCRegister Reg = getReg();
// Normalise to PPR
if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15)
Reg = Reg - AArch64::PN0 + AArch64::P0;
@@ -2336,13 +2336,12 @@ class AArch64Operand : public MCParsedAsmOperand {
}
static std::unique_ptr<AArch64Operand>
- CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx,
+ CreateReg(MCRegister Reg, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx,
RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg,
AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
- unsigned ShiftAmount = 0,
- unsigned HasExplicitAmount = false) {
+ unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) {
auto Op = std::make_unique<AArch64Operand>(k_Register, Ctx);
- Op->Reg.RegNum = RegNum;
+ Op->Reg.Reg = Reg;
Op->Reg.Kind = Kind;
Op->Reg.ElementWidth = 0;
Op->Reg.EqualityTy = EqTy;
@@ -2354,28 +2353,26 @@ class AArch64Operand : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<AArch64Operand>
- CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth,
- SMLoc S, SMLoc E, MCContext &Ctx,
- AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
- unsigned ShiftAmount = 0,
- unsigned HasExplicitAmount = false) {
+ static std::unique_ptr<AArch64Operand> CreateVectorReg(
+ MCRegister Reg, RegKind Kind, unsigned ElementWidth, SMLoc S, SMLoc E,
+ MCContext &Ctx, AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
+ unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) {
assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector ||
Kind == RegKind::SVEPredicateVector ||
Kind == RegKind::SVEPredicateAsCounter) &&
"Invalid vector kind");
- auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
+ auto Op = CreateReg(Reg, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
HasExplicitAmount);
Op->Reg.ElementWidth = ElementWidth;
return Op;
}
static std::unique_ptr<AArch64Operand>
- CreateVectorList(unsigned RegNum, unsigned Count, unsigned Stride,
+ CreateVectorList(MCRegister Reg, unsigned Count, unsigned Stride,
unsigned NumElements, unsigned ElementWidth,
RegKind RegisterKind, SMLoc S, SMLoc E, MCContext &Ctx) {
auto Op = std::make_unique<AArch64Operand>(k_VectorList, Ctx);
- Op->VectorList.RegNum = RegNum;
+ Op->VectorList.Reg = Reg;
Op->VectorList.Count = Count;
Op->VectorList.Stride = Stride;
Op->VectorList.NumElements = NumElements;
@@ -2586,10 +2583,10 @@ class AArch64Operand : public MCParsedAsmOperand {
}
static std::unique_ptr<AArch64Operand>
- CreateMatrixRegister(unsigned RegNum, unsigned ElementWidth, MatrixKind Kind,
+ CreateMatrixRegister(MCRegister Reg, unsigned ElementWidth, MatrixKind Kind,
SMLoc S, SMLoc E, MCContext &Ctx) {
auto Op = std::make_unique<AArch64Operand>(k_MatrixRegister, Ctx);
- Op->MatrixReg.RegNum = RegNum;
+ Op->MatrixReg.Reg = Reg;
Op->MatrixReg.ElementWidth = ElementWidth;
Op->MatrixReg.Kind = Kind;
Op->StartLoc = S;
@@ -2715,7 +2712,7 @@ void AArch64Operand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
break;
}
case k_Register:
- OS << "<register " << getReg() << ">";
+ OS << "<register " << getReg().id() << ">";
if (!getShiftExtendAmount() && !hasShiftExtendAmount())
break;
[[fallthrough]];
@@ -3048,53 +3045,53 @@ ParseStatus AArch64AsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
}
// Matches a register name or register alias previously defined by '.req'
-unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
- RegKind Kind) {
- unsigned RegNum = 0;
- if ((RegNum = matchSVEDataVectorRegName(Name)))
- return Kind == RegKind::SVEDataVector ? RegNum : 0;
+MCRegister AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
+ RegKind Kind) {
+ MCRegister Reg = MCRegister();
+ if ((Reg = matchSVEDataVectorRegName(Name)))
+ return Kind == RegKind::SVEDataVector ? Reg : MCRegister();
- if ((RegNum = matchSVEPredicateVectorRegName(Name)))
- return Kind == RegKind::SVEPredicateVector ? RegNum : 0;
+ if ((Reg = matchSVEPredicateVectorRegName(Name)))
+ return Kind == RegKind::SVEPredicateVector ? Reg : MCRegister();
- if ((RegNum = matchSVEPredicateAsCounterRegName(Name)))
- return Kind == RegKind::SVEPredicateAsCounter ? RegNum : 0;
+ if ((Reg = matchSVEPredicateAsCounterRegName(Name)))
+ return Kind == RegKind::SVEPredicateAsCounter ? Reg : MCRegister();
- if ((RegNum = MatchNeonVectorRegName(Name)))
- return Kind == RegKind::NeonVector ? RegNum : 0;
+ if ((Reg = MatchNeonVectorRegName(Name)))
+ return Kind == RegKind::NeonVector ? Reg : MCRegister();
- if ((RegNum = matchMatrixRegName(Name)))
- return Kind == RegKind::Matrix ? RegNum : 0;
+ if ((Reg = matchMatrixRegName(Name)))
+ return Kind == RegKind::Matrix ? Reg : MCRegister();
- if (Name.equals_insensitive("zt0"))
+ if (Name.equals_insensitive("zt0"))
return Kind == RegKind::LookupTable ? unsigned(AArch64::ZT0) : 0;
// The parsed register must be of RegKind Scalar
- if ((RegNum = MatchRegisterName(Name)))
- return (Kind == RegKind::Scalar) ? RegNum : 0;
+ if ((Reg = MatchRegisterName(Name)))
+ return (Kind == RegKind::Scalar) ? Reg : MCRegister();
- if (!RegNum) {
+ if (!Reg) {
// Handle a few common aliases of registers.
- if (auto RegNum = StringSwitch<unsigned>(Name.lower())
- .Case("fp", AArch64::FP)
- .Case("lr", AArch64::LR)
- .Case("x31", AArch64::XZR)
- .Case("w31", AArch64::WZR)
- .Default(0))
- return Kind == RegKind::Scalar ? RegNum : 0;
+ if (MCRegister Reg = StringSwitch<unsigned>(Name.lower())
+ .Case("fp", AArch64::FP)
+ .Case("lr", AArch64::LR)
+ .Case("x31", AArch64::XZR)
+ .Case("w31", AArch64::WZR)
+ .Default(0))
+ return Kind == RegKind::Scalar ? Reg : MCRegister();
// Check for aliases registered via .req. Canonicalize to lower case.
// That's more consistent since register names are case insensitive, and
// it's how the original entry was passed in from MC/MCParser/AsmParser.
auto Entry = RegisterReqs.find(Name.lower());
if (Entry == RegisterReqs.end())
- return 0;
+ return MCRegister();
- // set RegNum if the match is the right kind of register
+ // set Reg if the match is the right kind of register
if (Kind == Entry->getValue().first)
- RegNum = Entry->getValue().second;
+ Reg = Entry->getValue().second;
}
- return RegNum;
+ return Reg;
}
unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) {
@@ -3122,8 +3119,8 @@ ParseStatus AArch64AsmParser::tryParseScalarRegister(MCRegister &RegNum) {
return ParseStatus::NoMatch;
std::string lowerCase = Tok.getString().lower();
- unsigned Reg = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
- if (Reg == 0)
+ MCRegister Reg = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
+ if (!Reg)
return ParseStatus::NoMatch;
RegNum = Reg;
@@ -3667,7 +3664,7 @@ ParseStatus AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
}
// Try to parse matrix register.
- unsigned Reg = matchRegisterNameAlias(Name, RegKind::Matrix);
+ MCRegister Reg = matchRegisterNameAlias(Name, RegKind::Matrix);
if (!Reg)
return ParseStatus::NoMatch;
@@ -4130,12 +4127,12 @@ bool AArch64AsmParser::parseSyslAlias(StringRef Name, SMLoc NameLoc,
SMLoc startLoc = getLoc();
const AsmToken ®Tok = getTok();
StringRef reg = regTok.getString();
- unsigned RegNum = matchRegisterNameAlias(reg.lower(), RegKind::Scalar);
- if (!RegNum)
+ MCRegister Reg = matchRegisterNameAlias(reg.lower(), RegKind::Scalar);
+ if (!Reg)
return TokError("expected register operand");
Operands.push_back(AArch64Operand::CreateReg(
- RegNum, RegKind::Scalar, startLoc, getLoc(), getContext(), EqualsReg));
+ Reg, RegKind::Scalar, startLoc, getLoc(), getContext(), EqualsReg));
Lex(); // Eat token
if (parseToken(AsmToken::Comma))
@@ -4453,7 +4450,7 @@ ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg,
// a '.'.
size_t Start = 0, Next = Name.find('.');
StringRef Head = Name.slice(Start, Next);
- unsigned RegNum = matchRegisterNameAlias(Head, MatchKind);
+ MCRegister RegNum = matchRegisterNameAlias(Head, MatchKind);
if (RegNum) {
if (Next != StringRef::npos) {
@@ -4937,13 +4934,13 @@ ParseStatus AArch64AsmParser::tryParseZTOperand(OperandVector &Operands) {
const AsmToken &Tok = getTok();
std::string Name = Tok.getString().lower();
- unsigned RegNum = matchRegisterNameAlias(Name, RegKind::LookupTable);
+ MCRegister Reg = matchRegisterNameAlias(Name, RegKind::LookupTable);
- if (RegNum == 0)
+ if (!Reg)
return ParseStatus::NoMatch;
Operands.push_back(AArch64Operand::CreateReg(
- RegNum, RegKind::LookupTable, StartLoc, getLoc(), getContext()));
+ Reg, RegKind::LookupTable, StartLoc, getLoc(), getContext()));
Lex(); // Eat register.
// Check if register is followed by an index
@@ -7651,7 +7648,7 @@ bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
if (parseEOL())
return true;
- auto pair = std::make_pair(RegisterKind, (unsigned) RegNum);
+ auto pair = std::make_pair(RegisterKind, RegNum);
if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
Warning(L, "ignoring redefinition of register alias '" + Name + "'");
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