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[AMDGPU] Fix Inefficient S_CSELECT_B64 Sequence #167780

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[AMDGPU] Fix Inefficient S_CSELECT_B64 Sequence #167780

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e10e373
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linuxrocks123 Nov 12, 2025
bc28131
Fix
linuxrocks123 Nov 12, 2025
26dac49
This is backwards
linuxrocks123 Nov 12, 2025
76518b4
This is forwards.
linuxrocks123 Nov 12, 2025
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45 changes: 45 additions & 0 deletions llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include <optional>
Expand Down Expand Up @@ -66,6 +67,7 @@ class SIPeepholeSDWA {
MachineInstr *createSDWAVersion(MachineInstr &MI);
bool convertToSDWA(MachineInstr &MI, const SDWAOperandsVector &SDWAOperands);
void legalizeScalarOperands(MachineInstr &MI, const GCNSubtarget &ST) const;
bool strengthReduceCSelect64(MachineFunction &MF);

public:
bool run(MachineFunction &MF);
Expand Down Expand Up @@ -1362,6 +1364,46 @@ void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI,
}
}

bool SIPeepholeSDWA::strengthReduceCSelect64(MachineFunction &MF) {
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@arsenm arsenm Nov 13, 2025

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This has nothing to do with SDWA and doesn't belong here

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@linuxrocks123 linuxrocks123 Nov 13, 2025

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@arsenm our existing general peephole pass runs after register allocation, which is too late. This pass is running at about the right time. I could rename this pass or create a new pre-RA peephole pass. Which would you prefer?

bool Changed = false;

for (MachineBasicBlock &MBB : MF)
for (MachineInstr &MI : make_early_inc_range(MBB)) {
if (MI.getOpcode() != AMDGPU::S_CSELECT_B64 ||
!MI.getOperand(1).isImm() || !MI.getOperand(2).isImm() ||
(MI.getOperand(1).getImm() != 0 && MI.getOperand(2).getImm() != 0))
continue;

Register Reg = MI.getOperand(0).getReg();
MachineInstr *MustBeVCNDMASK = MRI->getOneNonDBGUser(Reg);
if (!MustBeVCNDMASK ||
MustBeVCNDMASK->getOpcode() != AMDGPU::V_CNDMASK_B32_e64 ||
!MustBeVCNDMASK->getOperand(1).isImm() ||
!MustBeVCNDMASK->getOperand(2).isImm())
continue;

MachineInstr *MustBeVREADFIRSTLANE =
MRI->getOneNonDBGUser(MustBeVCNDMASK->getOperand(0).getReg());
if (!MustBeVREADFIRSTLANE ||
MustBeVREADFIRSTLANE->getOpcode() != AMDGPU::V_READFIRSTLANE_B32)
continue;

unsigned CSelectZeroOpIdx = MI.getOperand(1).getImm() ? 2 : 1;

BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AMDGPU::S_CSELECT_B32),
MustBeVREADFIRSTLANE->getOperand(0).getReg())
.addImm(MustBeVCNDMASK->getOperand(CSelectZeroOpIdx + 2).getImm())
.addImm(
MustBeVCNDMASK->getOperand((CSelectZeroOpIdx == 1 ? 2 : 1) + 2)
.getImm())
.addReg(AMDGPU::SCC, RegState::Implicit);

MustBeVREADFIRSTLANE->eraseFromParent();
}

return Changed;
}

bool SIPeepholeSDWALegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
Expand Down Expand Up @@ -1436,6 +1478,9 @@ bool SIPeepholeSDWA::run(MachineFunction &MF) {
} while (Changed);
}

// Other target-specific SSA-form peephole optimizations
Ret |= strengthReduceCSelect64(MF);

return Ret;
}

Expand Down
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