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[AMDGPU] Make use of getFunction and getMF. NFC. #167872

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Nov 14, 2025
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[AMDGPU] Make use of getFunction and getMF. NFC. #167872

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356e32b
[AMDGPU] Make use of getFunction and getMF. NFC.
jayfoad Nov 13, 2025
87154d8
Also use getContext better
jayfoad Nov 13, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
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Expand Up @@ -65,7 +65,7 @@ recursivelyVisitUsers(GlobalValue &GV,
continue;

if (Instruction *I = dyn_cast<Instruction>(U)) {
Function *F = I->getParent()->getParent();
Function *F = I->getFunction();
if (!AMDGPU::isEntryFunctionCC(F->getCallingConv())) {
// FIXME: This is a horrible hack. We should always respect noinline,
// and just let us hit the error when we can't handle this.
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
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Expand Up @@ -1968,7 +1968,7 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
int NumBits = 0;

auto TRI = TII->getRegisterInfo();
auto &MRI = MI->getParent()->getParent()->getRegInfo();
auto &MRI = MI->getMF()->getRegInfo();
for (auto &Elt : Collection) {
auto Op = Elt->getInstr()->getOperand(0);
auto Size =
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -1998,7 +1998,7 @@ bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI,
}

bool AMDGPUInstructionSelector::selectInitWholeWave(MachineInstr &MI) const {
MachineFunction *MF = MI.getParent()->getParent();
MachineFunction *MF = MI.getMF();
SIMachineFunctionInfo *MFInfo = MF->getInfo<SIMachineFunctionInfo>();

MFInfo->setInitWholeWave();
Expand Down Expand Up @@ -3690,7 +3690,7 @@ bool AMDGPUInstructionSelector::selectBVHIntersectRayIntrinsic(
MI.getOpcode() == AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY ? 1 : 3;
MI.setDesc(TII.get(MI.getOperand(OpcodeOpIdx).getImm()));
MI.removeOperand(OpcodeOpIdx);
MI.addImplicitDefUseOperands(*MI.getParent()->getParent());
MI.addImplicitDefUseOperands(*MI.getMF());
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
}

Expand Down Expand Up @@ -3793,7 +3793,7 @@ bool AMDGPUInstructionSelector::selectSMFMACIntrin(MachineInstr &MI) const {
MI.removeOperand(4); // VDst_In
MI.removeOperand(1); // Intrinsic ID
MI.addOperand(VDst_In); // Readd VDst_In to the end
MI.addImplicitDefUseOperands(*MI.getParent()->getParent());
MI.addImplicitDefUseOperands(*MI.getMF());
const MCInstrDesc &MCID = MI.getDesc();
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
MI.getOperand(0).setIsEarlyClobber(true);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
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Expand Up @@ -845,7 +845,7 @@ bool AMDGPULibCalls::TDOFold(CallInst *CI, const FuncInfo &FInfo) {
return false;
}
}
LLVMContext &context = CI->getParent()->getParent()->getContext();
LLVMContext &context = CI->getFunction()->getContext();
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@jmmartinez jmmartinez Nov 13, 2025

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Suggested change
LLVMContext &context = CI->getFunction()->getContext();
LLVMContext &context = CI->getContext();

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@jayfoad jayfoad Nov 13, 2025

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I've made this change in a few places.

Constant *nval;
if (getArgType(FInfo) == AMDGPULibFunc::F32) {
SmallVector<float, 0> FVal;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
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Expand Up @@ -98,7 +98,7 @@ static void annotateGridSizeLoadWithRangeMD(LoadInst *Load,
}

static bool processUse(CallInst *CI, bool IsV5OrAbove) {
Function *F = CI->getParent()->getParent();
Function *F = CI->getFunction();

auto *MD = F->getMetadata("reqd_work_group_size");
const bool HasReqdWorkGroupSize = MD && MD->getNumOperands() == 3;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
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Expand Up @@ -243,7 +243,7 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {

int MCOpcode = TII->pseudoToMCOpcode(Opcode);
if (MCOpcode == -1) {
LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
"a target-specific version: " + Twine(MI->getOpcode()));
}
Expand Down Expand Up @@ -332,7 +332,7 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {

StringRef Err;
if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("Illegal instruction detected: " + Err);
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@jmmartinez jmmartinez Nov 13, 2025

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There is a emitGenericError that we could use:

void MachineInstr::emitGenericError(const Twine &Msg) const {
  const Function &Fn = getMF()->getFunction();
  Fn.getContext().diagnose(
      DiagnosticInfoGenericWithLoc(Msg, Fn, getDebugLoc()));
}

vs the current emitError:

void LLVMContext::emitError(const Twine &ErrorStr) {
  diagnose(DiagnosticInfoGeneric(ErrorStr));
}
 
void LLVMContext::emitError(const Instruction *I, const Twine &ErrorStr) {
  assert(I && "Invalid instruction");
  diagnose(DiagnosticInfoGeneric(I, ErrorStr));
}

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@jayfoad jayfoad Nov 13, 2025

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So this change would add location info to the diagnostic? That sounds good but not NFC so I'd prefer not to do it in this patch.

Comment on lines +335 to 336
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Suggested change
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("Illegal instruction detected: " + Err);
MI->emitGenericError("Illegal instruction detected: " + Err);

MI->print(errs());
}
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
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Expand Up @@ -177,8 +177,7 @@ void AMDGPUPreLegalizerCombinerImpl::applyClampI64ToI16(
MachineInstr &MI, const ClampI64ToI16MatchInfo &MatchInfo) const {

Register Src = MatchInfo.Origin;
assert(MI.getParent()->getParent()->getRegInfo().getType(Src) ==
LLT::scalar(64));
assert(MI.getMF()->getRegInfo().getType(Src) == LLT::scalar(64));
const LLT S32 = LLT::scalar(32);

auto Unmerge = B.buildUnmerge(S32, Src);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUPreloadKernelArguments.cpp
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Expand Up @@ -196,7 +196,7 @@ class PreloadKernelArgInfo {
SmallVector<std::pair<LoadInst *, unsigned>, 4> ImplicitArgLoads;
for (auto *U : ImplicitArgPtr->users()) {
Instruction *CI = dyn_cast<Instruction>(U);
if (!CI || CI->getParent()->getParent() != &F)
if (!CI || CI->getFunction() != &F)
continue;

for (auto *U : CI->users()) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
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Expand Up @@ -129,7 +129,7 @@ static StringRef getAsConstantStr(Value *V) {

static void diagnoseInvalidFormatString(const CallBase *CI) {
CI->getContext().diagnose(DiagnosticInfoUnsupported(
*CI->getParent()->getParent(),
*CI->getFunction(),
"printf format string must be a trivially resolved constant string "
"global variable",
CI->getDebugLoc()));
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
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Expand Up @@ -1378,7 +1378,7 @@ bool AMDGPUPromoteAllocaImpl::hasSufficientLocalMem(const Function &F) {
auto visitUsers = [&](const GlobalVariable *GV, const Constant *Val) -> bool {
for (const User *U : Val->users()) {
if (const Instruction *Use = dyn_cast<Instruction>(U)) {
if (Use->getParent()->getParent() == &F)
if (Use->getFunction() == &F)
return true;
} else {
const Constant *C = cast<Constant>(U);
Expand Down Expand Up @@ -1489,7 +1489,7 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToLDS(AllocaInst &I,
const DataLayout &DL = Mod->getDataLayout();
IRBuilder<> Builder(&I);

const Function &ContainingFunction = *I.getParent()->getParent();
const Function &ContainingFunction = *I.getFunction();
CallingConv::ID CC = ContainingFunction.getCallingConv();

// Don't promote the alloca to LDS for shader calling conventions as the work
Expand Down Expand Up @@ -1544,7 +1544,7 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToLDS(AllocaInst &I,

LLVM_DEBUG(dbgs() << "Promoting alloca to local memory\n");

Function *F = I.getParent()->getParent();
Function *F = I.getFunction();

Type *GVTy = ArrayType::get(I.getAllocatedType(), WorkGroupSize);
GlobalVariable *GV = new GlobalVariable(
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Expand Up @@ -468,7 +468,7 @@ RegisterBankInfo::InstructionMappings
AMDGPURegisterBankInfo::getInstrAlternativeMappings(
const MachineInstr &MI) const {

const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();


Expand Down Expand Up @@ -2409,7 +2409,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
if (DstBank == &AMDGPU::VCCRegBank)
break;

MachineFunction *MF = MI.getParent()->getParent();
MachineFunction *MF = MI.getMF();
ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);
LegalizerHelper Helper(*MF, ApplyBank, B);

Expand Down Expand Up @@ -2489,7 +2489,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
// There is no VALU abs instruction so we need to replace it with a sub and
// max combination.
if (SrcBank && SrcBank == &AMDGPU::VGPRRegBank) {
MachineFunction *MF = MI.getParent()->getParent();
MachineFunction *MF = MI.getMF();
ApplyRegBankMapping Apply(B, *this, MRI, &AMDGPU::VGPRRegBank);
LegalizerHelper Helper(*MF, Apply, B);

Expand Down Expand Up @@ -3604,7 +3604,7 @@ unsigned AMDGPURegisterBankInfo::getMappingType(const MachineRegisterInfo &MRI,
}

bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
Expand All @@ -3620,7 +3620,7 @@ bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {

const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());

Expand All @@ -3638,7 +3638,7 @@ AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {

const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());

Expand All @@ -3662,7 +3662,7 @@ AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {

const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());

Expand Down Expand Up @@ -3741,7 +3741,7 @@ AMDGPURegisterBankInfo::getValueMappingForPtr(const MachineRegisterInfo &MRI,
const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {

const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 2> OpdsMapping(2);
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
Expand Down Expand Up @@ -3831,7 +3831,7 @@ AMDGPURegisterBankInfo::getAGPROpMapping(Register Reg,
//
const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineFunction &MF = *MI.getMF();
const MachineRegisterInfo &MRI = MF.getRegInfo();

if (MI.isCopy() || MI.getOpcode() == AMDGPU::G_FREEZE) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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Expand Up @@ -282,7 +282,7 @@ bool AMDGPUSubtarget::isSingleLaneExecution(const Function &Func) const {
}

bool AMDGPUSubtarget::makeLIDRangeMetadata(Instruction *I) const {
Function *Kernel = I->getParent()->getParent();
Function *Kernel = I->getFunction();
unsigned MinSize = 0;
unsigned MaxSize = getFlatWorkGroupSizes(*Kernel).second;
bool IdQuery = false;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
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Expand Up @@ -523,7 +523,7 @@ static void replacesUsesOfGlobalInFunction(Function *Func, GlobalVariable *GV,
auto ReplaceUsesLambda = [Func](const Use &U) -> bool {
auto *V = U.getUser();
if (auto *Inst = dyn_cast<Instruction>(V)) {
auto *Func1 = Inst->getParent()->getParent();
auto *Func1 = Inst->getFunction();
if (Func == Func1)
return true;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
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Expand Up @@ -580,7 +580,7 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {

bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
const LiveRegSet *LiveRegsCopy) {
MRI = &MI.getParent()->getParent()->getRegInfo();
MRI = &MI.getMF()->getRegInfo();
LastTrackedMI = nullptr;
MBBEnd = MI.getParent()->end();
NextMI = &MI;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/GCNRegPressure.h
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Expand Up @@ -463,7 +463,7 @@ getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
}
llvm::sort(Indexes);

auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
auto &MRI = (*R.begin())->getMF()->getRegInfo();
DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> LiveRegMap;
SmallVector<SlotIndex, 32> LiveIdxs, SRLiveIdxs;
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Expand Down Expand Up @@ -493,13 +493,13 @@ getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
inline GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI,
const LiveIntervals &LIS) {
return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
MI.getParent()->getParent()->getRegInfo());
MI.getMF()->getRegInfo());
}

inline GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI,
const LiveIntervals &LIS) {
return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
MI.getParent()->getParent()->getRegInfo());
MI.getMF()->getRegInfo());
}

template <typename Range>
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
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Expand Up @@ -176,7 +176,7 @@ bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
}

bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const {
const MachineFunction *MF = MI.getParent()->getParent();
const MachineFunction *MF = MI.getMF();
return !AMDGPU::isCompute(MF->getFunction().getCallingConv()) &&
usesVertexCache(MI.getOpcode());
}
Expand All @@ -186,7 +186,7 @@ bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
}

bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const {
const MachineFunction *MF = MI.getParent()->getParent();
const MachineFunction *MF = MI.getMF();
return (AMDGPU::isCompute(MF->getFunction().getCallingConv()) &&
usesVertexCache(MI.getOpcode())) ||
usesTextureCache(MI.getOpcode());
Expand Down Expand Up @@ -948,15 +948,15 @@ bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
.setReg(Pred[2].getReg());
MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_W))
.setReg(Pred[2].getReg());
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
MachineInstrBuilder MIB(*MI.getMF(), MI);
MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
return true;
}

if (PIdx != -1) {
MachineOperand &PMO = MI.getOperand(PIdx);
PMO.setReg(Pred[2].getReg());
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
MachineInstrBuilder MIB(*MI.getMF(), MI);
MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
return true;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600MCInstLower.cpp
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Expand Up @@ -55,7 +55,7 @@ void R600AsmPrinter::emitInstruction(const MachineInstr *MI) {

StringRef Err;
if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("Illegal instruction detected: " + Err);
Comment on lines +58 to 59
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@jmmartinez jmmartinez Nov 13, 2025

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Suggested change
LLVMContext &C = MI->getMF()->getFunction().getContext();
C.emitError("Illegal instruction detected: " + Err);
MI->emitGenericError("Illegal instruction detected: " + Err);

MI->print(errs());
}
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
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Expand Up @@ -238,7 +238,7 @@ static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI,
const SIRegisterInfo *TRI,
const SIInstrInfo *TII) {
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
auto &Src = MI.getOperand(1);
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = Src.getReg();
Expand Down Expand Up @@ -930,7 +930,7 @@ bool SIFixSGPRCopies::lowerSpecialCase(MachineInstr &MI,
// s_mov_b32.
if (isSafeToFoldImmIntoCopy(&MI, MRI->getVRegDef(SrcReg), TII, SMovOp, Imm)) {
MI.getOperand(1).ChangeToImmediate(Imm);
MI.addImplicitDefUseOperands(*MI.getParent()->getParent());
MI.addImplicitDefUseOperands(*MI.getMF());
MI.setDesc(TII->get(SMovOp));
return true;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Expand Up @@ -1327,7 +1327,7 @@ void SIFoldOperandsImpl::foldOperand(
if (MovOp == AMDGPU::V_MOV_B16_t16_e64) {
const auto &SrcOp = UseMI->getOperand(UseOpIdx);
MachineOperand NewSrcOp(SrcOp);
MachineFunction *MF = UseMI->getParent()->getParent();
MachineFunction *MF = UseMI->getMF();
UseMI->removeOperand(1);
UseMI->addOperand(*MF, MachineOperand::CreateImm(0)); // src0_modifiers
UseMI->addOperand(NewSrcOp); // src0
Expand Down Expand Up @@ -1780,7 +1780,7 @@ bool SIFoldOperandsImpl::foldInstOperand(MachineInstr &MI,
if (CopiesToReplace.empty() && FoldList.empty())
return Changed;

MachineFunction *MF = MI.getParent()->getParent();
MachineFunction *MF = MI.getMF();
// Make sure we add EXEC uses to any new v_mov instructions created.
for (MachineInstr *Copy : CopiesToReplace)
Copy->addImplicitDefUseOperands(*MF);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -4052,7 +4052,7 @@ bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
if (!CI->isTailCall())
return false;

const Function *ParentFn = CI->getParent()->getParent();
const Function *ParentFn = CI->getFunction();
if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
return false;
return true;
Expand Down Expand Up @@ -17422,7 +17422,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
SDNode *Node) const {
const SIInstrInfo *TII = getSubtarget()->getInstrInfo();

MachineFunction *MF = MI.getParent()->getParent();
MachineFunction *MF = MI.getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();

if (TII->isVOP3(MI.getOpcode())) {
Expand Down
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