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[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension #168026

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[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension #168026

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aefd5bd
[RVV] Add test for missed VWMACC combine
Nov 14, 2025
16d98bc
[RISCV][DAGCombiner] Fix missed combines in combineOp_VLToVWOp_VL
Nov 15, 2025
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3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18300,8 +18300,7 @@ static SDValue combineOp_VLToVWOp_VL(SDNode *N,
}
}
for (std::pair<SDValue, SDValue> OldNewValues : ValuesToReplace) {
DAG.ReplaceAllUsesOfValueWith(OldNewValues.first, OldNewValues.second);
DCI.AddToWorklist(OldNewValues.second.getNode());
DCI.CombineTo(OldNewValues.first.getNode(), OldNewValues.second);
}
return InputRootReplacement;
}
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54 changes: 54 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/combine-vl-vw-macc.ll
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@@ -0,0 +1,54 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64

define void @matmul_min(ptr %vptr, ptr %scalars, ptr %acc0_ptr, ptr %acc1_ptr) {
; CHECK-LABEL: matmul_min:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a4, 64
; CHECK-NEXT: li a5, 32
; CHECK-NEXT: vsetvli zero, a5, e8, m2, ta, ma
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: lb a0, 0(a1)
; CHECK-NEXT: lb a1, 1(a1)
; CHECK-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-NEXT: vle8.v v8, (a2)
; CHECK-NEXT: vle8.v v12, (a3)
; CHECK-NEXT: vsetvli zero, a5, e8, m2, ta, ma
; CHECK-NEXT: vwmacc.vx v8, a0, v16
; CHECK-NEXT: vwmacc.vx v12, a1, v16
; CHECK-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: vse8.v v12, (a3)
; CHECK-NEXT: ret
entry:
%acc0 = load <32 x i16>, ptr %acc0_ptr, align 1
%acc1 = load <32 x i16>, ptr %acc1_ptr, align 1

%v8 = load <32 x i8>, ptr %vptr, align 1
%v16 = sext <32 x i8> %v8 to <32 x i16>

%s0_ptr = getelementptr i8, ptr %scalars, i32 0
%s0_i8 = load i8, ptr %s0_ptr, align 1
%s0_i16 = sext i8 %s0_i8 to i16
%tmp0 = insertelement <32 x i16> poison, i16 %s0_i16, i32 0
%splat0 = shufflevector <32 x i16> %tmp0, <32 x i16> poison, <32 x i32> zeroinitializer
%mul0 = mul <32 x i16> %splat0, %v16
%add0 = add <32 x i16> %mul0, %acc0

%s1_ptr = getelementptr i8, ptr %scalars, i32 1
%s1_i8 = load i8, ptr %s1_ptr, align 1
%s1_i16 = sext i8 %s1_i8 to i16
%tmp1 = insertelement <32 x i16> poison, i16 %s1_i16, i32 0
%splat1 = shufflevector <32 x i16> %tmp1, <32 x i16> poison, <32 x i32> zeroinitializer
%mul1 = mul <32 x i16> %splat1, %v16
%add1 = add <32 x i16> %mul1, %acc1

store <32 x i16> %add0, ptr %acc0_ptr, align 1
store <32 x i16> %add1, ptr %acc1_ptr, align 1

ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
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