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[X86] Enable APX and AVX10.2 on NVL #168061

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Merged
merged 6 commits into from
Nov 17, 2025
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[X86] Enable APX and AVX10.2 on NVL #168061

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928c4e4
Enable APX and AVX10.2 on NVL
mikolaj-pirog Nov 14, 2025
26e473a
Fix test
mikolaj-pirog Nov 14, 2025
6d35b7d
Fix test
mikolaj-pirog Nov 14, 2025
8904d11
Reviewer suggestions
mikolaj-pirog Nov 17, 2025
a997903
Shuffle check around
mikolaj-pirog Nov 17, 2025
fba4231
Change comment
mikolaj-pirog Nov 17, 2025
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74 changes: 62 additions & 12 deletions clang/test/Preprocessor/predefined-arch-macros.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2525,16 +2525,33 @@
// RUN: %clang -march=wildcatlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M32,CHECK_ARLS_M32,CHECK_NKL_M32
// RUN: %clang -march=novalake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M32,CHECK_ARLS_M32,CHECK_NVL_M32,CHECK_NKL_M32
// RUN: %clang -march=clearwaterforest -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32,CHECK_ARLS_M32,CHECK_NVL_M32,CHECK_UMSR_M32,CHECK_NKL_M32
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32,CHECK_ARLS_M32,CHECK_UMSR_M32,CHECK_CWF_M32,CHECK_NKL_M32
// RUN: %clang -march=novalake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M32,CHECK_ARLS_M32,CHECK_CWF_M32,CHECK_NVL_M32,CHECK_NKL_M32
// CHECK_ARL_M32: #define __ADX__ 1
// CHECK_ARL_M32: #define __AES__ 1
// CHECK_ARL_M32: #define __AVX2__ 1
// CHECK_ARL_M32-NOT: AVX512
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@phoebewang phoebewang Nov 15, 2025

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Move this below AVX2

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@mikolaj-pirog mikolaj-pirog Nov 15, 2025

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If avx2 is on the 2536 line the test fails

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@phoebewang phoebewang Nov 16, 2025

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I see, it's a bit tricky to leverage order to solve NVL inheritance problem. Do we have a better choice? Otherwise, add a comment for future reference.

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@phoebewang phoebewang Nov 17, 2025

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Think twice, I found we will lose coverage for all targets, because AVX512 won't be in front of AVX2, no matter they support AVX512 or not.

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@phoebewang phoebewang Nov 17, 2025

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If there's no other way around, it's better just to remove it.

// CHECK_NVL_M32: #define __AVX10_1_512__ 1
// CHECK_NVL_M32: #define __AVX10_1__ 1
// CHECK_NVL_M32: #define __AVX10_2_512__ 1
// CHECK_NVL_M32: #define __AVX10_2__ 1
// CHECK_ARL_M32: #define __AVX2__ 1
// CHECK_NVL_M32: #define __AVX512BF16__ 1
// CHECK_NVL_M32: #define __AVX512BITALG__ 1
// CHECK_NVL_M32: #define __AVX512BW__ 1
// CHECK_NVL_M32: #define __AVX512CD__ 1
// CHECK_NVL_M32: #define __AVX512DQ__ 1
// CHECK_NVL_M32: #define __AVX512FP16__ 1
// CHECK_NVL_M32: #define __AVX512F__ 1
// CHECK_NVL_M32: #define __AVX512IFMA__ 1
// CHECK_NVL_M32: #define __AVX512VBMI2__ 1
// CHECK_NVL_M32: #define __AVX512VBMI__ 1
// CHECK_NVL_M32: #define __AVX512VL__ 1
// CHECK_NVL_M32: #define __AVX512VNNI__ 1
// CHECK_NVL_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ARL_M32: #define __AVXIFMA__ 1
// CHECK_ARL_M32: #define __AVXNECONVERT__ 1
// CHECK_ARL_M32-NOT: #define __AVXVNNIINT16__ 1
Expand All @@ -2544,11 +2561,13 @@
// CHECK_ARL_M32: #define __AVX__ 1
// CHECK_ARL_M32: #define __BMI2__ 1
// CHECK_ARL_M32: #define __BMI__ 1
// CHECK_NVL_M32: #define __CCMP__ 1
// CHECK_ARLS_M32-NOT: __CLDEMOTE__
// CHECK_SRF_M32: #define __CLDEMOTE__ 1
// CHECK_ARL_M32: #define __CLFLUSHOPT__ 1
// CHECK_ARL_M32: #define __CLWB__ 1
// CHECK_ARL_M32: #define __CMPCCXADD__ 1
// CHECK_NVL_M32: #define __EGPR__ 1
// CHECK_ARL_M32: #define __ENQCMD__ 1
// CHECK_ARL_M32: #define __F16C__ 1
// CHECK_ARL_M32: #define __FMA__ 1
Expand All @@ -2564,15 +2583,20 @@
// CHECK_ARL_M32: #define __MOVBE__ 1
// CHECK_ARL_M32: #define __MOVDIR64B__ 1
// CHECK_ARL_M32: #define __MOVDIRI__ 1
// CHECK_NVL_M32: #define __MOVRS__ 1
// CHECK_NVL_M32: #define __NDD__ 1
// CHECK_NVL_M32: #define __NF__ 1
// CHECK_ARL_M32: #define __PCLMUL__ 1
// CHECK_ARL_M32: #define __PCONFIG__ 1
// CHECK_ARL_M32: #define __PKU__ 1
// CHECK_ARL_M32: #define __POPCNT__ 1
// CHECK_NVL_M32: #define __PPX__ 1
// CHECK_ARL_M32-NOT: #define __PREFETCHI__ 1
// CHECK_ARLS_M32-NOT: #define __PREFETCHI__ 1
// CHECK_NVL_M32: #define __PREFETCHI__ 1
// CHECK_CWF_M32: #define __PREFETCHI__ 1
// CHECK_ARL_M32: #define __PRFCHW__ 1
// CHECK_ARL_M32: #define __PTWRITE__ 1
// CHECK_NVL_M32: #define __PUSH2POP2__ 1
// CHECK_ARL_M32-NOT: #define __RAOINT__ 1
// CHECK_ARL_M32: #define __RDPID__ 1
// CHECK_ARL_M32: #define __RDRND__ 1
Expand Down Expand Up @@ -2607,6 +2631,7 @@
// CHECK_ARL_M32: #define __XSAVEOPT__ 1
// CHECK_ARL_M32: #define __XSAVES__ 1
// CHECK_ARL_M32: #define __XSAVE__ 1
// CHECK_NVL_M32: #define __ZU__ 1
// CHECK_ARL_M32: #define __corei7 1
// CHECK_ARL_M32: #define __corei7__ 1
// CHECK_ARL_M32: #define __i386 1
Expand Down Expand Up @@ -2635,16 +2660,33 @@
// RUN: %clang -march=wildcatlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M64,CHECK_ARLS_M64,CHECK_NKL_M64
// RUN: %clang -march=novalake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M64,CHECK_ARLS_M64,CHECK_NVL_M64,CHECK_NKL_M64
// RUN: %clang -march=clearwaterforest -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M64,CHECK_SRF_M64,CHECK_ARLS_M64,CHECK_NVL_M64,CHECK_UMSR_M64,CHECK_NKL_M64
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64,CHECK_ARLS_M64,CHECK_UMSR_M64,CHECK_CWF_M64,CHECK_NKL_M64
// RUN: %clang -march=novalake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_ARL_M64,CHECK_ARLS_M64,CHECK_CWF_M64,CHECK_NVL_M64,CHECK_NKL_M64
// CHECK_ARL_M64: #define __ADX__ 1
// CHECK_ARL_M64: #define __AES__ 1
// CHECK_ARL_M64: #define __AVX2__ 1
// CHECK_ARL_M64-NOT: AVX512
// CHECK_NVL_M64: #define __AVX10_1_512__ 1
// CHECK_NVL_M64: #define __AVX10_1__ 1
// CHECK_NVL_M64: #define __AVX10_2_512__ 1
// CHECK_NVL_M64: #define __AVX10_2__ 1
// CHECK_ARL_M64: #define __AVX2__ 1
// CHECK_NVL_M64: #define __AVX512BF16__ 1
// CHECK_NVL_M64: #define __AVX512BITALG__ 1
// CHECK_NVL_M64: #define __AVX512BW__ 1
// CHECK_NVL_M64: #define __AVX512CD__ 1
// CHECK_NVL_M64: #define __AVX512DQ__ 1
// CHECK_NVL_M64: #define __AVX512FP16__ 1
// CHECK_NVL_M64: #define __AVX512F__ 1
// CHECK_NVL_M64: #define __AVX512IFMA__ 1
// CHECK_NVL_M64: #define __AVX512VBMI2__ 1
// CHECK_NVL_M64: #define __AVX512VBMI__ 1
// CHECK_NVL_M64: #define __AVX512VL__ 1
// CHECK_NVL_M64: #define __AVX512VNNI__ 1
// CHECK_NVL_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ARL_M64: #define __AVXIFMA__ 1
// CHECK_ARL_M64: #define __AVXNECONVERT__ 1
// CHECK_ARL_M64-NOT: #define __AVXVNNIINT16__ 1
Expand All @@ -2654,11 +2696,13 @@
// CHECK_ARL_M64: #define __AVX__ 1
// CHECK_ARL_M64: #define __BMI2__ 1
// CHECK_ARL_M64: #define __BMI__ 1
// CHECK_NVL_M64: #define __CCMP__ 1
// CHECK_ARLS_M64-NOT: __CLDEMOTE__
// CHECK_SRF_M64: #define __CLDEMOTE__ 1
// CHECK_ARL_M64: #define __CLFLUSHOPT__ 1
// CHECK_ARL_M64: #define __CLWB__ 1
// CHECK_ARL_M64: #define __CMPCCXADD__ 1
// CHECK_NVL_M64: #define __EGPR__ 1
// CHECK_ARL_M64: #define __ENQCMD__ 1
// CHECK_ARL_M64: #define __F16C__ 1
// CHECK_ARL_M64: #define __FMA__ 1
Expand All @@ -2674,15 +2718,20 @@
// CHECK_ARL_M64: #define __MOVBE__ 1
// CHECK_ARL_M64: #define __MOVDIR64B__ 1
// CHECK_ARL_M64: #define __MOVDIRI__ 1
// CHECK_NVL_M64: #define __MOVRS__ 1
// CHECK_NVL_M64: #define __NDD__ 1
// CHECK_NVL_M64: #define __NF__ 1
// CHECK_ARL_M64: #define __PCLMUL__ 1
// CHECK_ARL_M64: #define __PCONFIG__ 1
// CHECK_ARL_M64: #define __PKU__ 1
// CHECK_ARL_M64: #define __POPCNT__ 1
// CHECK_NVL_M64: #define __PPX__ 1
// CHECK_ARL_M64-NOT: #define __PREFETCHI__ 1
// CHECK_ARLS_M64-NOT: #define __PREFETCHI__ 1
// CHECK_NVL_M64: #define __PREFETCHI__ 1
// CHECK_CWF_M64: #define __PREFETCHI__ 1
// CHECK_ARL_M64: #define __PRFCHW__ 1
// CHECK_ARL_M64: #define __PTWRITE__ 1
// CHECK_NVL_M64: #define __PUSH2POP2__ 1
// CHECK_ARL_M64-NOT: #define __RAOINT__ 1
// CHECK_ARL_M64: #define __RDPID__ 1
// CHECK_ARL_M64: #define __RDRND__ 1
Expand Down Expand Up @@ -2718,6 +2767,7 @@
// CHECK_ARL_M64: #define __XSAVEOPT__ 1
// CHECK_ARL_M64: #define __XSAVES__ 1
// CHECK_ARL_M64: #define __XSAVE__ 1
// CHECK_NVL_M64: #define __ZU__ 1
// CHECK_ARL_M64: #define __amd64 1
// CHECK_ARL_M64: #define __amd64__ 1
// CHECK_ARL_M64: #define __corei7 1
Expand Down
12 changes: 11 additions & 1 deletion llvm/lib/Target/X86/X86.td
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Expand Up @@ -1334,8 +1334,18 @@ def ProcessorFeatures {
!listremove(ARLSFeatures, [FeatureWIDEKL]);

// Novalake
list<SubtargetFeature> NVLAdditionalFeatures = [FeatureAVX10_2,
FeatureMOVRS,
FeatureEGPR,
FeaturePush2Pop2,
FeaturePPX,
FeatureNF,
FeatureNDD,
FeatureZU,
FeatureCCMP,
FeaturePREFETCHI];
list<SubtargetFeature> NVLFeatures =
!listconcat(PTLFeatures, [FeaturePREFETCHI]);
!listconcat(PTLFeatures, NVLAdditionalFeatures);

// Clearwaterforest
list<SubtargetFeature> CWFAdditionalFeatures = [FeaturePREFETCHI,
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/TargetParser/X86TargetParser.cpp
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Expand Up @@ -176,7 +176,9 @@ constexpr FeatureBitset FeaturesArrowlakeS =
constexpr FeatureBitset FeaturesPantherlake =
(FeaturesArrowlakeS ^ FeatureWIDEKL);
constexpr FeatureBitset FeaturesNovalake =
FeaturesPantherlake | FeaturePREFETCHI;
FeaturesPantherlake | FeaturePREFETCHI | FeatureAVX10_2 | FeatureMOVRS |
FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX |
FeatureNDD | FeatureNF;
constexpr FeatureBitset FeaturesClearwaterforest =
(FeaturesSierraforest ^ FeatureWIDEKL) | FeatureAVXVNNIINT16 |
FeatureSHA512 | FeatureSM3 | FeatureSM4 | FeaturePREFETCHI | FeatureUSERMSR;
Expand Down
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