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[LoongArch] TableGen-erate SDNode descriptions #168129

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1f0f01b
LoongArch
s-barannikov Nov 16, 2024
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s-barannikov Nov 14, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/LoongArch/CMakeLists.txt
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Expand Up @@ -10,6 +10,7 @@ tablegen(LLVM LoongArchGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM LoongArchGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM LoongArchGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM LoongArchGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM LoongArchGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM LoongArchGenSubtargetInfo.inc -gen-subtarget)

add_public_tablegen_target(LoongArchCommonTableGen)
Expand All @@ -27,6 +28,7 @@ add_llvm_target(LoongArchCodeGen
LoongArchMergeBaseOffset.cpp
LoongArchOptWInstrs.cpp
LoongArchRegisterInfo.cpp
LoongArchSelectionDAGInfo.cpp
LoongArchSubtarget.cpp
LoongArchTargetMachine.cpp
LoongArchTargetTransformInfo.cpp
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5 changes: 5 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
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Expand Up @@ -30,13 +30,18 @@ def SDT_LoongArchFRSQRTE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
// ISD::BRCOND is custom-lowered to LoongArchISD::BRCOND for floating-point
// comparisons to prevent recursive lowering.
def loongarch_brcond : SDNode<"LoongArchISD::BRCOND", SDTBrcond, [SDNPHasChain]>;

// FPR<->GPR transfer operations
def loongarch_movgr2fr_w
: SDNode<"LoongArchISD::MOVGR2FR_W", SDT_LoongArchMOVGR2FR_W>;
def loongarch_movgr2fr_w_la64
: SDNode<"LoongArchISD::MOVGR2FR_W_LA64", SDT_LoongArchMOVGR2FR_W_LA64>;
def loongarch_movfr2gr_s_la64
: SDNode<"LoongArchISD::MOVFR2GR_S_LA64", SDT_LoongArchMOVFR2GR_S_LA64>;

def loongarch_ftint : SDNode<"LoongArchISD::FTINT", SDT_LoongArchFTINT>;

// Floating point approximate reciprocal operation
def loongarch_frecipe : SDNode<"LoongArchISD::FRECIPE", SDT_LoongArchFRECIPE>;
def loongarch_frsqrte : SDNode<"LoongArchISD::FRSQRTE", SDT_LoongArchFRSQRTE>;

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1 change: 1 addition & 0 deletions llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
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Expand Up @@ -20,6 +20,7 @@ def SDT_LoongArchMOVGR2FR_D_LO_HI
: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;

// FPR<->GPR transfer operations
def loongarch_movgr2fr_d
: SDNode<"LoongArchISD::MOVGR2FR_D", SDT_LoongArchMOVGR2FR_D>;
def loongarch_movgr2fr_d_lo_hi
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1 change: 1 addition & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
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Expand Up @@ -14,6 +14,7 @@
#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H

#include "LoongArch.h"
#include "LoongArchSelectionDAGInfo.h"
#include "LoongArchTargetMachine.h"
#include "llvm/CodeGen/SelectionDAGISel.h"

Expand Down
124 changes: 4 additions & 120 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Expand Up @@ -15,6 +15,7 @@
#include "LoongArch.h"
#include "LoongArchMachineFunctionInfo.h"
#include "LoongArchRegisterInfo.h"
#include "LoongArchSelectionDAGInfo.h"
#include "LoongArchSubtarget.h"
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
Expand Down Expand Up @@ -1712,7 +1713,7 @@ lowerVECTOR_SHUFFLE_VSHUF4I(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,

// Return vshuf4i.d
if (VT == MVT::v2f64 || VT == MVT::v2i64)
return DAG.getNode(LoongArchISD::VSHUF4I, DL, VT, V1, V2,
return DAG.getNode(LoongArchISD::VSHUF4I_D, DL, VT, V1, V2,
DAG.getConstant(Imm, DL, GRLenVT));

return DAG.getNode(LoongArchISD::VSHUF4I, DL, VT, V1,
Expand Down Expand Up @@ -4459,7 +4460,7 @@ SDValue LoongArchTargetLowering::lowerShiftRightParts(SDValue Op,

// Returns the opcode of the target-specific SDNode that implements the 32-bit
// form of the given Opcode.
static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode) {
static unsigned getLoongArchWOpcode(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
Expand Down Expand Up @@ -4495,7 +4496,7 @@ static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode) {
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp,
unsigned ExtOpc = ISD::ANY_EXTEND) {
SDLoc DL(N);
LoongArchISD::NodeType WOpcode = getLoongArchWOpcode(N->getOpcode());
unsigned WOpcode = getLoongArchWOpcode(N->getOpcode());
SDValue NewOp0, NewRes;

switch (NumOp) {
Expand Down Expand Up @@ -7483,123 +7484,6 @@ bool LoongArchTargetLowering::allowsMisalignedMemoryAccesses(
return true;
}

const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((LoongArchISD::NodeType)Opcode) {
case LoongArchISD::FIRST_NUMBER:
break;

#define NODE_NAME_CASE(node) \
case LoongArchISD::node: \
return "LoongArchISD::" #node;

// TODO: Add more target-dependent nodes later.
NODE_NAME_CASE(CALL)
NODE_NAME_CASE(CALL_MEDIUM)
NODE_NAME_CASE(CALL_LARGE)
NODE_NAME_CASE(RET)
NODE_NAME_CASE(TAIL)
NODE_NAME_CASE(TAIL_MEDIUM)
NODE_NAME_CASE(TAIL_LARGE)
NODE_NAME_CASE(SELECT_CC)
NODE_NAME_CASE(BR_CC)
NODE_NAME_CASE(BRCOND)
NODE_NAME_CASE(SLL_W)
NODE_NAME_CASE(SRA_W)
NODE_NAME_CASE(SRL_W)
NODE_NAME_CASE(BSTRINS)
NODE_NAME_CASE(BSTRPICK)
NODE_NAME_CASE(MOVGR2FR_W)
NODE_NAME_CASE(MOVGR2FR_W_LA64)
NODE_NAME_CASE(MOVGR2FR_D)
NODE_NAME_CASE(MOVGR2FR_D_LO_HI)
NODE_NAME_CASE(MOVFR2GR_S_LA64)
NODE_NAME_CASE(FTINT)
NODE_NAME_CASE(BUILD_PAIR_F64)
NODE_NAME_CASE(SPLIT_PAIR_F64)
NODE_NAME_CASE(REVB_2H)
NODE_NAME_CASE(REVB_2W)
NODE_NAME_CASE(BITREV_4B)
NODE_NAME_CASE(BITREV_8B)
NODE_NAME_CASE(BITREV_W)
NODE_NAME_CASE(ROTR_W)
NODE_NAME_CASE(ROTL_W)
NODE_NAME_CASE(DIV_W)
NODE_NAME_CASE(DIV_WU)
NODE_NAME_CASE(MOD_W)
NODE_NAME_CASE(MOD_WU)
NODE_NAME_CASE(CLZ_W)
NODE_NAME_CASE(CTZ_W)
NODE_NAME_CASE(DBAR)
NODE_NAME_CASE(IBAR)
NODE_NAME_CASE(BREAK)
NODE_NAME_CASE(SYSCALL)
NODE_NAME_CASE(CRC_W_B_W)
NODE_NAME_CASE(CRC_W_H_W)
NODE_NAME_CASE(CRC_W_W_W)
NODE_NAME_CASE(CRC_W_D_W)
NODE_NAME_CASE(CRCC_W_B_W)
NODE_NAME_CASE(CRCC_W_H_W)
NODE_NAME_CASE(CRCC_W_W_W)
NODE_NAME_CASE(CRCC_W_D_W)
NODE_NAME_CASE(CSRRD)
NODE_NAME_CASE(CSRWR)
NODE_NAME_CASE(CSRXCHG)
NODE_NAME_CASE(IOCSRRD_B)
NODE_NAME_CASE(IOCSRRD_H)
NODE_NAME_CASE(IOCSRRD_W)
NODE_NAME_CASE(IOCSRRD_D)
NODE_NAME_CASE(IOCSRWR_B)
NODE_NAME_CASE(IOCSRWR_H)
NODE_NAME_CASE(IOCSRWR_W)
NODE_NAME_CASE(IOCSRWR_D)
NODE_NAME_CASE(CPUCFG)
NODE_NAME_CASE(MOVGR2FCSR)
NODE_NAME_CASE(MOVFCSR2GR)
NODE_NAME_CASE(CACOP_D)
NODE_NAME_CASE(CACOP_W)
NODE_NAME_CASE(VSHUF)
NODE_NAME_CASE(VPICKEV)
NODE_NAME_CASE(VPICKOD)
NODE_NAME_CASE(VPACKEV)
NODE_NAME_CASE(VPACKOD)
NODE_NAME_CASE(VILVL)
NODE_NAME_CASE(VILVH)
NODE_NAME_CASE(VSHUF4I)
NODE_NAME_CASE(VREPLVEI)
NODE_NAME_CASE(VREPLGR2VR)
NODE_NAME_CASE(XVPERMI)
NODE_NAME_CASE(XVPERM)
NODE_NAME_CASE(XVREPLVE0)
NODE_NAME_CASE(XVREPLVE0Q)
NODE_NAME_CASE(XVINSVE0)
NODE_NAME_CASE(VPICK_SEXT_ELT)
NODE_NAME_CASE(VPICK_ZEXT_ELT)
NODE_NAME_CASE(VREPLVE)
NODE_NAME_CASE(VALL_ZERO)
NODE_NAME_CASE(VANY_ZERO)
NODE_NAME_CASE(VALL_NONZERO)
NODE_NAME_CASE(VANY_NONZERO)
NODE_NAME_CASE(FRECIPE)
NODE_NAME_CASE(FRSQRTE)
NODE_NAME_CASE(VSLLI)
NODE_NAME_CASE(VSRLI)
NODE_NAME_CASE(VBSLL)
NODE_NAME_CASE(VBSRL)
NODE_NAME_CASE(VLDREPL)
NODE_NAME_CASE(VMSKLTZ)
NODE_NAME_CASE(VMSKGEZ)
NODE_NAME_CASE(VMSKEQZ)
NODE_NAME_CASE(VMSKNEZ)
NODE_NAME_CASE(XVMSKLTZ)
NODE_NAME_CASE(XVMSKGEZ)
NODE_NAME_CASE(XVMSKEQZ)
NODE_NAME_CASE(XVMSKNEZ)
NODE_NAME_CASE(VHADDW)
}
#undef NODE_NAME_CASE
return nullptr;
}

//===----------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
Expand Down
176 changes: 0 additions & 176 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.h
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Expand Up @@ -21,179 +21,6 @@

namespace llvm {
class LoongArchSubtarget;
namespace LoongArchISD {
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,

// TODO: add more LoongArchISDs
CALL,
CALL_MEDIUM,
CALL_LARGE,
RET,
TAIL,
TAIL_MEDIUM,
TAIL_LARGE,

// Select
SELECT_CC,

// Branch
BR_CC,
BRCOND,

// 32-bit shifts, directly matching the semantics of the named LoongArch
// instructions.
SLL_W,
SRA_W,
SRL_W,

ROTL_W,
ROTR_W,

// unsigned 32-bit integer division
DIV_W,
MOD_W,
DIV_WU,
MOD_WU,

// FPR<->GPR transfer operations
MOVGR2FR_W,
MOVGR2FR_W_LA64,
MOVGR2FR_D,
MOVGR2FR_D_LO_HI,
MOVFR2GR_S_LA64,
MOVFCSR2GR,
MOVGR2FCSR,

FTINT,

// Build and split F64 pair
BUILD_PAIR_F64,
SPLIT_PAIR_F64,

// Bit counting operations
CLZ_W,
CTZ_W,

BSTRINS,
BSTRPICK,

// Byte-swapping and bit-reversal
REVB_2H,
REVB_2W,
BITREV_4B,
BITREV_8B,
BITREV_W,

// Intrinsic operations start ============================================
BREAK,
CACOP_D,
CACOP_W,
DBAR,
IBAR,
SYSCALL,

// CRC check operations
CRC_W_B_W,
CRC_W_H_W,
CRC_W_W_W,
CRC_W_D_W,
CRCC_W_B_W,
CRCC_W_H_W,
CRCC_W_W_W,
CRCC_W_D_W,

CSRRD,

// Write new value to CSR and return old value.
// Operand 0: A chain pointer.
// Operand 1: The new value to write.
// Operand 2: The address of the required CSR.
// Result 0: The old value of the CSR.
// Result 1: The new chain pointer.
CSRWR,

// Similar to CSRWR but with a write mask.
// Operand 0: A chain pointer.
// Operand 1: The new value to write.
// Operand 2: The write mask.
// Operand 3: The address of the required CSR.
// Result 0: The old value of the CSR.
// Result 1: The new chain pointer.
CSRXCHG,

// IOCSR access operations
IOCSRRD_B,
IOCSRRD_W,
IOCSRRD_H,
IOCSRRD_D,
IOCSRWR_B,
IOCSRWR_H,
IOCSRWR_W,
IOCSRWR_D,

// Read CPU configuration information operation
CPUCFG,

// Vector Shuffle
VREPLVE,
VSHUF,
VPICKEV,
VPICKOD,
VPACKEV,
VPACKOD,
VILVL,
VILVH,
VSHUF4I,
VREPLVEI,
VREPLGR2VR,
XVPERMI,
XVPERM,
XVREPLVE0,
XVREPLVE0Q,
XVINSVE0,

// Extended vector element extraction
VPICK_SEXT_ELT,
VPICK_ZEXT_ELT,

// Vector comparisons
VALL_ZERO,
VANY_ZERO,
VALL_NONZERO,
VANY_NONZERO,

// Floating point approximate reciprocal operation
FRECIPE,
FRSQRTE,

// Vector logicial left / right shift by immediate
VSLLI,
VSRLI,

// Vector byte logicial left / right shift
VBSLL,
VBSRL,

// Scalar load broadcast to vector
VLDREPL,

// Vector mask set by condition
VMSKLTZ,
VMSKGEZ,
VMSKEQZ,
VMSKNEZ,
XVMSKLTZ,
XVMSKGEZ,
XVMSKEQZ,
XVMSKNEZ,

// Vector Horizontal Addition with Widening‌
VHADDW

// Intrinsic operations end =============================================
};
} // end namespace LoongArchISD

class LoongArchTargetLowering : public TargetLowering {
const LoongArchSubtarget &Subtarget;
Expand All @@ -213,9 +40,6 @@ class LoongArchTargetLowering : public TargetLowering {

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;

// This method returns the name of a target specific DAG node.
const char *getTargetNodeName(unsigned Opcode) const override;

// Lower incoming arguments, copy physregs into vregs.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
Expand Down
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