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AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 #168166

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Merged
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Nov 15, 2025
+1,225 −1,237
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AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 #168166

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7 changes: 6 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2941,10 +2941,15 @@ def : GCNPat <
>;

def : GCNPat <
(i64 (zext i32:$src)),
(i64 (UniformUnaryFrag<zext> i32:$src)),
(REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 (i32 0)), sub1)
>;

def : GCNPat <
(i64 (zext i32:$src)),
(REG_SEQUENCE VReg_64, $src, sub0, (V_MOV_B32_e32 (i32 0)), sub1)
>;

def : GCNPat <
(i64 (anyext i32:$src)),
(REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1)
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
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Expand Up @@ -2549,17 +2549,17 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1164_ITERATIVE-LABEL: add_i64_varying:
; GFX1164_ITERATIVE: ; %bb.0: ; %entry
; GFX1164_ITERATIVE-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, 0
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_ITERATIVE-NEXT: v_and_b32_e32 v3, 0x3ff, v0
; GFX1164_ITERATIVE-NEXT: s_mov_b64 s[0:1], exec
; GFX1164_ITERATIVE-NEXT: s_mov_b64 s[6:7], 0
; GFX1164_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1164_ITERATIVE-NEXT: .LBB5_1: ; %ComputeLoop
; GFX1164_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1164_ITERATIVE-NEXT: s_ctz_i32_b64 s2, s[0:1]
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s2
; GFX1164_ITERATIVE-NEXT: v_readlane_b32 s8, v3, s2
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: v_readlane_b32 s3, v3, s2
; GFX1164_ITERATIVE-NEXT: v_readlane_b32 s8, v2, s2
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s2
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s2
; GFX1164_ITERATIVE-NEXT: s_add_u32 s6, s6, s3
Expand Down Expand Up @@ -2606,16 +2606,16 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1132_ITERATIVE-LABEL: add_i64_varying:
; GFX1132_ITERATIVE: ; %bb.0: ; %entry
; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x3ff, v0
; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
; GFX1132_ITERATIVE-NEXT: s_mov_b32 s0, exec_lo
; GFX1132_ITERATIVE-NEXT: s_mov_b64 s[6:7], 0
; GFX1132_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1132_ITERATIVE-NEXT: .LBB5_1: ; %ComputeLoop
; GFX1132_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1132_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1132_ITERATIVE-NEXT: v_readlane_b32 s2, v2, s1
; GFX1132_ITERATIVE-NEXT: v_readlane_b32 s3, v3, s1
; GFX1132_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s1
; GFX1132_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s1
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s1
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1132_ITERATIVE-NEXT: s_add_u32 s6, s6, s2
Expand Down Expand Up @@ -2659,17 +2659,17 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1264_ITERATIVE-LABEL: add_i64_varying:
; GFX1264_ITERATIVE: ; %bb.0: ; %entry
; GFX1264_ITERATIVE-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1264_ITERATIVE-NEXT: v_mov_b32_e32 v3, 0
; GFX1264_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
; GFX1264_ITERATIVE-NEXT: v_and_b32_e32 v3, 0x3ff, v0
; GFX1264_ITERATIVE-NEXT: s_mov_b64 s[0:1], exec
; GFX1264_ITERATIVE-NEXT: s_mov_b64 s[6:7], 0
; GFX1264_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1264_ITERATIVE-NEXT: .LBB5_1: ; %ComputeLoop
; GFX1264_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264_ITERATIVE-NEXT: s_ctz_i32_b64 s8, s[0:1]
; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s3, v3, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s2, v2, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s8
; GFX1264_ITERATIVE-NEXT: s_lshl_b64 s[8:9], 1, s8
Expand Down Expand Up @@ -2714,7 +2714,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1232_ITERATIVE-LABEL: add_i64_varying:
; GFX1232_ITERATIVE: ; %bb.0: ; %entry
; GFX1232_ITERATIVE-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x3ff, v0
; GFX1232_ITERATIVE-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
; GFX1232_ITERATIVE-NEXT: s_mov_b32 s0, exec_lo
; GFX1232_ITERATIVE-NEXT: s_mov_b64 s[6:7], 0
; GFX1232_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
Expand All @@ -2723,8 +2723,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
; GFX1232_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s3, v3, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v2, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1232_ITERATIVE-NEXT: s_lshl_b32 s1, 1, s1
Expand Down Expand Up @@ -6930,15 +6930,15 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1164_ITERATIVE-LABEL: sub_i64_varying:
; GFX1164_ITERATIVE: ; %bb.0: ; %entry
; GFX1164_ITERATIVE-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, 0
; GFX1164_ITERATIVE-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164_ITERATIVE-NEXT: s_mov_b64 s[0:1], exec
; GFX1164_ITERATIVE-NEXT: s_mov_b64 s[8:9], 0
; GFX1164_ITERATIVE-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1164_ITERATIVE-NEXT: .LBB11_1: ; %ComputeLoop
; GFX1164_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1164_ITERATIVE-NEXT: s_ctz_i32_b64 s2, s[0:1]
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: v_readlane_b32 s3, v0, s2
; GFX1164_ITERATIVE-NEXT: v_readlane_b32 s6, v1, s2
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v5, s9, s2
Expand Down Expand Up @@ -7087,17 +7087,17 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1264_ITERATIVE-LABEL: sub_i64_varying:
; GFX1264_ITERATIVE: ; %bb.0: ; %entry
; GFX1264_ITERATIVE-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1264_ITERATIVE-NEXT: v_mov_b32_e32 v3, 0
; GFX1264_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
; GFX1264_ITERATIVE-NEXT: v_and_b32_e32 v3, 0x3ff, v0
; GFX1264_ITERATIVE-NEXT: s_mov_b64 s[0:1], exec
; GFX1264_ITERATIVE-NEXT: s_mov_b64 s[6:7], 0
; GFX1264_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1264_ITERATIVE-NEXT: .LBB11_1: ; %ComputeLoop
; GFX1264_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264_ITERATIVE-NEXT: s_ctz_i32_b64 s8, s[0:1]
; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s3, v3, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s2, v2, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s8
; GFX1264_ITERATIVE-NEXT: s_lshl_b64 s[8:9], 1, s8
Expand Down Expand Up @@ -7142,7 +7142,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
;
; GFX1232_ITERATIVE-LABEL: sub_i64_varying:
; GFX1232_ITERATIVE: ; %bb.0: ; %entry
; GFX1232_ITERATIVE-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x3ff, v0
; GFX1232_ITERATIVE-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
; GFX1232_ITERATIVE-NEXT: s_mov_b32 s0, exec_lo
; GFX1232_ITERATIVE-NEXT: s_mov_b64 s[6:7], 0
; GFX1232_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
Expand All @@ -7151,8 +7151,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
; GFX1232_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s3, v3, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v2, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1232_ITERATIVE-NEXT: s_lshl_b32 s1, 1, s1
Expand Down
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