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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86ExpandPseudo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -638,10 +638,10 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
Opc = X86::TCVTROWPS2PHLrri;
break;
case X86::PTILEMOVROWrreV:
Opc = X86::TILEMOVROWrre;
Opc = X86::TILEMOVROWrte;
break;
case X86::PTILEMOVROWrriV:
Opc = X86::TILEMOVROWrri;
Opc = X86::TILEMOVROWrti;
break;
default:
llvm_unreachable("Unexpected Opcode");
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -38246,7 +38246,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Opc = X86::TCVTROWPS2PHLrri;
break;
case X86::PTILEMOVROWrri:
Opc = X86::TILEMOVROWrri;
Opc = X86::TILEMOVROWrti;
break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
Expand Down Expand Up @@ -38284,7 +38284,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Opc = X86::TCVTROWPS2PHLrre;
break;
case X86::PTILEMOVROWrre:
Opc = X86::TILEMOVROWrre;
Opc = X86::TILEMOVROWrte;
break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/X86/X86InstrAMX.td
Original file line number Diff line number Diff line change
Expand Up @@ -475,22 +475,22 @@ defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>;
defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>;
defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;

multiclass m_tilemovrow {
multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> {
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
let SchedRW = [WriteSystem] in {
def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
(ins TILE:$src1, u8imm:$src2),
"tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[]>, TA,PD, EVEX, EVEX_V512;
def rre : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TA, PD, EVEX, EVEX_V512;
def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
(ins TILE:$src1, GR32:$src2),
"tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[]>, T8,PD, EVEX, VVVV, EVEX_V512;
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, T8, PD, EVEX, VVVV, EVEX_V512;
}
} // HasAMXAVX512, HasAVX10_2, In64BitMode
}

defm TILEMOVROW : m_tilemovrow;
defm TILEMOVROW : AMXAVX512_TILEMOVE<0x07, 0x4A, "tilemovrow">;

let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
let SchedRW = [WriteSystem] in {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -1733,8 +1733,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ]
Key: TILELOADDRS_EVEX: [ 0.00 0.00 ]
Key: TILELOADDT: [ 0.00 0.00 ]
Key: TILELOADD_EVEX: [ 0.00 0.00 ]
Key: TILEMOVROWrre: [ 0.00 0.00 ]
Key: TILEMOVROWrri: [ 0.00 0.00 ]
Key: TILEMOVROWrte: [ 0.00 0.00 ]
Key: TILEMOVROWrti: [ 0.00 0.00 ]
Key: TILERELEASE: [ 0.00 0.00 ]
Key: TILESTORED: [ 0.00 0.00 ]
Key: TILESTORED_EVEX: [ 0.00 0.00 ]
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -1733,8 +1733,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ]
Key: TILELOADDRS_EVEX: [ 0.00 0.00 ]
Key: TILELOADDT: [ 0.00 0.00 ]
Key: TILELOADD_EVEX: [ 0.00 0.00 ]
Key: TILEMOVROWrre: [ 0.00 0.00 ]
Key: TILEMOVROWrri: [ 0.00 0.00 ]
Key: TILEMOVROWrte: [ 0.00 0.00 ]
Key: TILEMOVROWrti: [ 0.00 0.00 ]
Key: TILERELEASE: [ 0.00 0.00 ]
Key: TILESTORED: [ 0.00 0.00 ]
Key: TILESTORED_EVEX: [ 0.00 0.00 ]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
Original file line number Diff line number Diff line change
Expand Up @@ -1734,8 +1734,8 @@ TILELOADDRST 1731
TILELOADDRS_EVEX 1732
TILELOADDT 1733
TILELOADD_EVEX 1734
TILEMOVROWrre 1735
TILEMOVROWrri 1736
TILEMOVROWrte 1735
TILEMOVROWrti 1736
TILERELEASE 1737
TILESTORED 1738
TILESTORED_EVEX 1739
Expand Down
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