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[SelectionDAG] Fix AArch64 machine verifier bug when expanding LOOP_DEPENDENCE_MASK #168221

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Merged
merged 2 commits into from
Nov 15, 2025
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[SelectionDAG] Fix AArch64 machine verifier bug when expanding LOOP_DEPENDENCE_MASK #168221

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ef258e1
Pre-commit test (NFC)
AZero13 Nov 15, 2025
bf6ae88
[SelectionDAG] Fix AArch64 machine verifier bug when expanding LOOP_D…
AZero13 Nov 15, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1829,7 +1829,7 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
// If the difference is positive then some elements may alias
EVT CmpVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
Diff.getValueType());
SDValue Zero = DAG.getTargetConstant(0, DL, PtrVT);
SDValue Zero = DAG.getConstant(0, DL, PtrVT);
SDValue Cmp = DAG.getSetCC(DL, CmpVT, Diff, Zero,
IsReadAfterWrite ? ISD::SETEQ : ISD::SETLE);

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Expand Up @@ -413,7 +413,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
SDValue Diff = DAG.getNode(ISD::SUB, DL, PtrVT, SinkValue, SourceValue);
EVT CmpVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
Diff.getValueType());
SDValue Zero = DAG.getTargetConstant(0, DL, PtrVT);
SDValue Zero = DAG.getConstant(0, DL, PtrVT);
return DAG.getNode(ISD::OR, DL, CmpVT,
DAG.getSetCC(DL, CmpVT, Diff, EltSize, ISD::SETGE),
DAG.getSetCC(DL, CmpVT, Diff, Zero, ISD::SETEQ));
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10 changes: 4 additions & 6 deletions llvm/test/CodeGen/AArch64/alias_mask.ll
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Expand Up @@ -793,9 +793,8 @@ define <1 x i1> @whilewr_8_scalarize(ptr %a, ptr %b) {
; CHECK-LABEL: whilewr_8_scalarize:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: ccmp x8, #0, #4, le
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: cmn x8, #1
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 1)
Expand Down Expand Up @@ -845,9 +844,8 @@ define <1 x i1> @whilerw_8_scalarize(ptr %a, ptr %b) {
; CHECK-LABEL: whilerw_8_scalarize:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub x8, x1, x0
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: ccmp x8, #0, #4, le
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: cmn x8, #1
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = call <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr %a, ptr %b, i64 1)
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45 changes: 45 additions & 0 deletions llvm/test/CodeGen/AArch64/loop-dependence-mask-ccmp.ll
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@@ -0,0 +1,45 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs -stop-after=finalize-isel %s -o - | FileCheck %s

; Regression test for a bug where getTargetConstant(0) was used instead of
; getConstant(0) in ScalarizeVecRes_LOOP_DEPENDENCE_MASK, causing instruction
; selection to incorrectly generate CCMPXr (register form) with an immediate
; operand instead of CCMPXi (immediate form).
;

define <1 x i1> @test_war_mask_ccmp(ptr %a, ptr %b) {
; CHECK-LABEL: name: test_war_mask_ccmp
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64common = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri killed [[SUBSXrr]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 1)
ret <1 x i1> %0
}

define <1 x i1> @test_raw_mask_ccmp(ptr %a, ptr %b) {
; CHECK-LABEL: name: test_raw_mask_ccmp
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64common = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri killed [[SUBSXrr]], 1, 0, implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = call <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr %a, ptr %b, i64 1)
ret <1 x i1> %0
}

declare <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr, ptr, i64)
declare <1 x i1> @llvm.loop.dependence.raw.mask.v1i1(ptr, ptr, i64)
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