[RegAlloc] Relax the split constrain on MBB prolog

llvm/lib/CodeGen/RegAllocGreedy.cpp

@@ -773,8 +773,7 @@ bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
       // Abort if the spill cannot be inserted at the MBB' start
       if (((BC.Entry == SpillPlacement::MustSpill) ||
            (BC.Entry == SpillPlacement::PrefSpill)) &&
-          SlotIndex::isEarlierInstr(BI.FirstInstr,
-                                    SA->getFirstSplitPoint(BC.Number)))
+          !SA->canSplitBeforeProlog(BC.Number))
         return false;
     }
 
@@ -829,11 +828,7 @@ bool RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
     BCS[B].Number = Number;
 
     // Abort if the spill cannot be inserted at the MBB' start
-    MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
-    auto FirstNonDebugInstr = MBB->getFirstNonDebugInstr();
-    if (FirstNonDebugInstr != MBB->end() &&
-        SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*FirstNonDebugInstr),
-                                  SA->getFirstSplitPoint(Number)))
+    if (!SA->canSplitBeforeProlog(Number))
       return false;
     // Interference for the live-in value.
     if (Intf.first() <= Indexes->getMBBStartIdx(Number))

llvm/lib/CodeGen/SplitKit.cpp

@@ -147,6 +147,34 @@ InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
   return LIS.getInstructionFromIndex(LIP);
 }
 
+bool InsertPointAnalysis::canSplitBeforeProlog(const LiveInterval &CurLI,
+                                               const MachineBasicBlock &MBB) {
+  const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
+
+  for (auto &MI : MBB) {
+    if (MI.isPHI() || MI.isPosition() || MI.isDebugInstr() ||
+        MI.isPseudoProbe())
+      continue;
+
+    if (!TII->isBasicBlockPrologue(MI))
+      return true;
+
+    for (auto &MO : MI.operands()) {
+      if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+        continue;
+
+      const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+      const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
+      const TargetRegisterClass *RC = MRI.getRegClass(MO.getReg());
+      const TargetRegisterClass *CurRC = MRI.getRegClass(CurLI.reg());
+      if (TRI->getCommonSubClass(RC, CurRC))
+        return false;
+    }
+  }
+
+  return true;
+}
+
 //===----------------------------------------------------------------------===//
 //                                 Split Analysis
 //===----------------------------------------------------------------------===//

llvm/lib/CodeGen/SplitKit.h

@@ -89,6 +89,9 @@ class LLVM_LIBRARY_VISIBILITY InsertPointAnalysis {
     return Res;
   }
 
+  /// Return true if we can split \pCurLI before \pMBB's prolog.
+  bool canSplitBeforeProlog(const LiveInterval &CurLI,
+                            const MachineBasicBlock &MBB);
 };
 
 /// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
@@ -247,6 +250,11 @@ class LLVM_LIBRARY_VISIBILITY SplitAnalysis {
   SlotIndex getFirstSplitPoint(unsigned Num) {
     return IPA.getFirstInsertPoint(*MF.getBlockNumbered(Num));
   }
+
+  bool canSplitBeforeProlog(unsigned Num) {
+    MachineBasicBlock *BB = MF.getBlockNumbered(Num);
+    return IPA.canSplitBeforeProlog(*CurLI, *BB);
+  }
 };
 
 /// SplitEditor - Edit machine code and LiveIntervals for live range