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[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes are in use. #168387

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Merged
merged 1 commit into from
Nov 20, 2025
Merged

[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes are in use. #168387

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -1774,14 +1774,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,

if (Subtarget->hasSVEB16B16() &&
Subtarget->isNonStreamingSVEorSME2Available()) {
setOperationAction(ISD::FADD, VT, Legal);
setOperationAction(ISD::FADD, VT, Custom);
setOperationAction(ISD::FMA, VT, Custom);
setOperationAction(ISD::FMAXIMUM, VT, Custom);
setOperationAction(ISD::FMAXNUM, VT, Custom);
setOperationAction(ISD::FMINIMUM, VT, Custom);
setOperationAction(ISD::FMINNUM, VT, Custom);
setOperationAction(ISD::FMUL, VT, Legal);
setOperationAction(ISD::FSUB, VT, Legal);
setOperationAction(ISD::FMUL, VT, Custom);
setOperationAction(ISD::FSUB, VT, Custom);
}
}

Expand Down
2 changes: 0 additions & 2 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -2439,8 +2439,6 @@ multiclass sve_fp_3op_u_zd_bfloat<bits<3> opc, string asm, SDPatternOperator op>
def NAME : sve_fp_3op_u_zd<0b00, opc, asm, ZPR16>;

def : SVE_2_Op_Pat<nxv8bf16, op, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
def : SVE_2_Op_Pat<nxv4bf16, op, nxv4bf16, nxv4bf16, !cast<Instruction>(NAME)>;
def : SVE_2_Op_Pat<nxv2bf16, op, nxv2bf16, nxv2bf16, !cast<Instruction>(NAME)>;
}

multiclass sve_fp_3op_u_zd_ftsmul<bits<3> opc, string asm, SDPatternOperator op> {
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18 changes: 12 additions & 6 deletions llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
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Expand Up @@ -56,7 +56,8 @@ define <vscale x 2 x bfloat> @fadd_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x
;
; B16B16-LABEL: fadd_nxv2bf16:
; B16B16: // %bb.0:
; B16B16-NEXT: bfadd z0.h, z0.h, z1.h
; B16B16-NEXT: ptrue p0.d
; B16B16-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; B16B16-NEXT: ret
%res = fadd <vscale x 2 x bfloat> %a, %b
ret <vscale x 2 x bfloat> %res
Expand All @@ -74,7 +75,8 @@ define <vscale x 4 x bfloat> @fadd_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x
;
; B16B16-LABEL: fadd_nxv4bf16:
; B16B16: // %bb.0:
; B16B16-NEXT: bfadd z0.h, z0.h, z1.h
; B16B16-NEXT: ptrue p0.s
; B16B16-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; B16B16-NEXT: ret
%res = fadd <vscale x 4 x bfloat> %a, %b
ret <vscale x 4 x bfloat> %res
Expand Down Expand Up @@ -525,7 +527,8 @@ define <vscale x 2 x bfloat> @fmul_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x
;
; B16B16-LABEL: fmul_nxv2bf16:
; B16B16: // %bb.0:
; B16B16-NEXT: bfmul z0.h, z0.h, z1.h
; B16B16-NEXT: ptrue p0.d
; B16B16-NEXT: bfmul z0.h, p0/m, z0.h, z1.h
; B16B16-NEXT: ret
%res = fmul <vscale x 2 x bfloat> %a, %b
ret <vscale x 2 x bfloat> %res
Expand All @@ -543,7 +546,8 @@ define <vscale x 4 x bfloat> @fmul_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x
;
; B16B16-LABEL: fmul_nxv4bf16:
; B16B16: // %bb.0:
; B16B16-NEXT: bfmul z0.h, z0.h, z1.h
; B16B16-NEXT: ptrue p0.s
; B16B16-NEXT: bfmul z0.h, p0/m, z0.h, z1.h
; B16B16-NEXT: ret
%res = fmul <vscale x 4 x bfloat> %a, %b
ret <vscale x 4 x bfloat> %res
Expand Down Expand Up @@ -672,7 +676,8 @@ define <vscale x 2 x bfloat> @fsub_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x
;
; B16B16-LABEL: fsub_nxv2bf16:
; B16B16: // %bb.0:
; B16B16-NEXT: bfsub z0.h, z0.h, z1.h
; B16B16-NEXT: ptrue p0.d
; B16B16-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; B16B16-NEXT: ret
%res = fsub <vscale x 2 x bfloat> %a, %b
ret <vscale x 2 x bfloat> %res
Expand All @@ -690,7 +695,8 @@ define <vscale x 4 x bfloat> @fsub_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x
;
; B16B16-LABEL: fsub_nxv4bf16:
; B16B16: // %bb.0:
; B16B16-NEXT: bfsub z0.h, z0.h, z1.h
; B16B16-NEXT: ptrue p0.s
; B16B16-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; B16B16-NEXT: ret
%res = fsub <vscale x 4 x bfloat> %a, %b
ret <vscale x 4 x bfloat> %res
Expand Down
36 changes: 10 additions & 26 deletions llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
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Expand Up @@ -311,8 +311,7 @@ define <vscale x 8 x bfloat> @fadd_sel_nxv8bf16(<vscale x 8 x bfloat> %a, <vscal
;
; SVE-B16B16-LABEL: fadd_sel_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfadd z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT: ret
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> zeroinitializer
%fadd = fadd nsz <vscale x 8 x bfloat> %a, %sel
Expand Down Expand Up @@ -341,8 +340,7 @@ define <vscale x 8 x bfloat> @fsub_sel_nxv8bf16(<vscale x 8 x bfloat> %a, <vscal
;
; SVE-B16B16-LABEL: fsub_sel_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfsub z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT: ret
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> zeroinitializer
%fsub = fsub <vscale x 8 x bfloat> %a, %sel
Expand Down Expand Up @@ -371,8 +369,7 @@ define <vscale x 8 x bfloat> @fadd_sel_negzero_nxv8bf16(<vscale x 8 x bfloat> %a
;
; SVE-B16B16-LABEL: fadd_sel_negzero_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfadd z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT: ret
%nz = fneg <vscale x 8 x bfloat> zeroinitializer
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %nz
Expand Down Expand Up @@ -402,8 +399,7 @@ define <vscale x 8 x bfloat> @fsub_sel_negzero_nxv8bf16(<vscale x 8 x bfloat> %a
;
; SVE-B16B16-LABEL: fsub_sel_negzero_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfsub z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; SVE-B16B16-NEXT: ret
%nz = fneg <vscale x 8 x bfloat> zeroinitializer
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %nz
Expand Down Expand Up @@ -490,9 +486,7 @@ define <vscale x 8 x bfloat> @fsub_sel_fmul_nxv8bf16(<vscale x 8 x bfloat> %a, <
;
; SVE-B16B16-LABEL: fsub_sel_fmul_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT: bfsub z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT: ret
%fmul = fmul <vscale x 8 x bfloat> %b, %c
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
Expand Down Expand Up @@ -532,9 +526,7 @@ define <vscale x 8 x bfloat> @fadd_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %
;
; SVE-B16B16-LABEL: fadd_sel_fmul_nsz_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT: bfadd z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT: ret
%fmul = fmul <vscale x 8 x bfloat> %b, %c
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
Expand Down Expand Up @@ -574,9 +566,7 @@ define <vscale x 8 x bfloat> @fsub_sel_fmul_nsz_nxv8bf16(<vscale x 8 x bfloat> %
;
; SVE-B16B16-LABEL: fsub_sel_fmul_nsz_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT: bfsub z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT: ret
%fmul = fmul <vscale x 8 x bfloat> %b, %c
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %fmul, <vscale x 8 x bfloat> zeroinitializer
Expand Down Expand Up @@ -616,9 +606,7 @@ define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nxv8bf16(<vscale x 8 x bfloa
;
; SVE-B16B16-LABEL: fadd_sel_fmul_negzero_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT: bfadd z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT: ret
%fmul = fmul <vscale x 8 x bfloat> %b, %c
%nz = fneg <vscale x 8 x bfloat> zeroinitializer
Expand Down Expand Up @@ -711,9 +699,7 @@ define <vscale x 8 x bfloat> @fadd_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x b
;
; SVE-B16B16-LABEL: fadd_sel_fmul_negzero_nsz_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT: bfadd z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfmla z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT: ret
%fmul = fmul <vscale x 8 x bfloat> %b, %c
%nz = fneg <vscale x 8 x bfloat> zeroinitializer
Expand Down Expand Up @@ -754,9 +740,7 @@ define <vscale x 8 x bfloat> @fsub_sel_fmul_negzero_nsz_nxv8bf16(<vscale x 8 x b
;
; SVE-B16B16-LABEL: fsub_sel_fmul_negzero_nsz_nxv8bf16:
; SVE-B16B16: // %bb.0:
; SVE-B16B16-NEXT: bfmul z1.h, z1.h, z2.h
; SVE-B16B16-NEXT: bfsub z1.h, z0.h, z1.h
; SVE-B16B16-NEXT: mov z0.h, p0/m, z1.h
; SVE-B16B16-NEXT: bfmls z0.h, p0/m, z1.h, z2.h
; SVE-B16B16-NEXT: ret
%fmul = fmul <vscale x 8 x bfloat> %b, %c
%nz = fneg <vscale x 8 x bfloat> zeroinitializer
Expand Down
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