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[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. #169529

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[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. #169529

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[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG.
topperc Nov 25, 2025
68a4e8f
Merge remote-tracking branch 'origin/main' into pr/zilsd-non-volatile
topperc Nov 25, 2025
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9 changes: 7 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8404,7 +8404,12 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
if (Store->isTruncatingStore())
return SDValue();

if (Store->getAlign() < Subtarget.getZilsdAlign())
// Expand non-volatile or misaligned stores.
// Keep stores of 0 since that doesn't constrain the register allocator.
if (!(Store->isVolatile() ||
(isa<ConstantSDNode>(StoredVal) &&
cast<ConstantSDNode>(StoredVal)->isZero())) ||
Store->getAlign() < Subtarget.getZilsdAlign())
return SDValue();

SDLoc DL(Op);
Expand Down Expand Up @@ -14803,7 +14808,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
assert(Subtarget.hasStdExtZilsd() && !Subtarget.is64Bit() &&
"Unexpected custom legalisation");

if (Ld->getAlign() < Subtarget.getZilsdAlign())
if (!Ld->isVolatile() || Ld->getAlign() < Subtarget.getZilsdAlign())
return;

SDLoc DL(N);
Expand Down
51 changes: 19 additions & 32 deletions llvm/test/CodeGen/RISCV/zilsd.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,10 @@
define i64 @load(ptr %a) nounwind {
; CHECK-LABEL: load:
; CHECK: # %bb.0:
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: ld a0, 80(a0)
; CHECK-NEXT: ld zero, 0(a2)
; CHECK-NEXT: lw a2, 80(a0)
; CHECK-NEXT: lw a1, 84(a0)
; CHECK-NEXT: ld zero, 0(a0)
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: ret
%1 = getelementptr i64, ptr %a, i32 10
%2 = load i64, ptr %1
Expand Down Expand Up @@ -44,10 +45,10 @@ define i64 @load_align4(ptr %a) nounwind {
define void @store(ptr %a, i64 %b) nounwind {
; CHECK-LABEL: store:
; CHECK: # %bb.0:
; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: sd a2, 0(a0)
; CHECK-NEXT: sd a2, 88(a0)
; CHECK-NEXT: sw a1, 0(a0)
; CHECK-NEXT: sw a2, 4(a0)
; CHECK-NEXT: sw a1, 88(a0)
; CHECK-NEXT: sw a2, 92(a0)
Comment on lines +48 to +51
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@4vtomat 4vtomat Nov 26, 2025

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Curious that does this also considered a regression in terms of latency since it turns 2 loads to 4 loads?
Or it doesn't matter since latency of sd is 2 * sw

; CHECK-NEXT: ret
store i64 %b, ptr %a
%1 = getelementptr i64, ptr %a, i32 11
Expand All @@ -56,25 +57,11 @@ define void @store(ptr %a, i64 %b) nounwind {
}

define void @store_align4(ptr %a, i64 %b) nounwind {
; SLOW-LABEL: store_align4:
; SLOW: # %bb.0:
; SLOW-NEXT: sw a1, 88(a0)
; SLOW-NEXT: sw a2, 92(a0)
; SLOW-NEXT: ret
;
; FAST-LABEL: store_align4:
; FAST: # %bb.0:
; FAST-NEXT: mv a3, a2
; FAST-NEXT: mv a2, a1
; FAST-NEXT: sd a2, 88(a0)
; FAST-NEXT: ret
;
; 4BYTEALIGN-LABEL: store_align4:
; 4BYTEALIGN: # %bb.0:
; 4BYTEALIGN-NEXT: mv a3, a2
; 4BYTEALIGN-NEXT: mv a2, a1
; 4BYTEALIGN-NEXT: sd a2, 88(a0)
; 4BYTEALIGN-NEXT: ret
; CHECK-LABEL: store_align4:
; CHECK: # %bb.0:
; CHECK-NEXT: sw a1, 88(a0)
; CHECK-NEXT: sw a2, 92(a0)
; CHECK-NEXT: ret
%1 = getelementptr i64, ptr %a, i32 11
store i64 %b, ptr %1, align 4
ret void
Expand Down Expand Up @@ -158,9 +145,8 @@ define void @store_unaligned(ptr %p, i64 %v) {
;
; FAST-LABEL: store_unaligned:
; FAST: # %bb.0:
; FAST-NEXT: mv a3, a2
; FAST-NEXT: mv a2, a1
; FAST-NEXT: sd a2, 0(a0)
; FAST-NEXT: sw a1, 0(a0)
; FAST-NEXT: sw a2, 4(a0)
; FAST-NEXT: ret
;
; 4BYTEALIGN-LABEL: store_unaligned:
Expand Down Expand Up @@ -213,10 +199,11 @@ define void @large_offset(ptr nocapture %p, i64 %d) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a1, 4
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: ld a2, -384(a0)
; CHECK-NEXT: lw a2, -384(a0)
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@topperc topperc Nov 25, 2025

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This is a regression. x10 is already allocated. We pick x11 for the odd register first, but this can't pair since x10 is already used. So we pick x12 for the even but don't revisit the odd.

; CHECK-NEXT: lw a1, -380(a0)
; CHECK-NEXT: addi a2, a2, 1
; CHECK-NEXT: seqz a1, a2
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: seqz a3, a2
; CHECK-NEXT: add a3, a1, a3
; CHECK-NEXT: sd a2, -384(a0)
; CHECK-NEXT: ret
entry:
Expand Down
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