Skip to content

Conversation

@topperc
Copy link
Collaborator

@topperc topperc commented Nov 25, 2025

No description provided.

@llvmbot
Copy link
Member

llvmbot commented Nov 25, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/169538.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+3-5)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 263d6a1fc2220..a5aef4bea46ab 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -895,11 +895,9 @@ bool RISCVRegisterInfo::getRegAllocationHints(
       // Check if this register matches the even/odd requirement
       bool IsOdd = (RegNum % 2 != 0);
 
-      // Verify the pair register exists and is in the same register class
-      // TODO: Skip unallocatable registers: we need to prevent any of odd/even
-      // to be reserved, so if we need odd, we need to check if corresponding
-      // even is preserved, vice versa.
-      if ((WantOdd && IsOdd) || (!WantOdd && !IsOdd))
+      // Don't provide hints that are paired to a reserved register.
+      MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
+      if (WantOdd == IsOdd && !MRI->isReserved(Paired))
         Hints.push_back(PhysReg);
     }
   }

Copy link
Member

@lenary lenary left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I guess it's good there are no test changes from this.

@topperc topperc merged commit eab23e1 into llvm:main Nov 25, 2025
10 of 11 checks passed
@topperc topperc deleted the pr/zilsd-reserved branch November 25, 2025 18:58
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants