[AMDGPU] Add scaffolding for ML focused scheduling strategy #169616
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| //===-- AMDGPUMLSchedStrategy.cpp - ML-focused Scheduler Strategy ---------===// | ||
| // | ||
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| // | ||
| /// \file | ||
| /// ML-focused scheduling strategy for AMDGPU. | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
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| #include "AMDGPUMLSchedStrategy.h" | ||
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| using namespace llvm; | ||
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| AMDGPUMLSchedStrategy::AMDGPUMLSchedStrategy(const MachineSchedContext *C) | ||
| : GCNSchedStrategy(C) { | ||
| SchedStages.push_back(GCNSchedStageID::ILPInitialSchedule); | ||
| SchedStages.push_back(GCNSchedStageID::PreRARematerialize); | ||
| // Use more accurate GCN pressure trackers. | ||
| UseGCNTrackers = true; | ||
| } | ||
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| void AMDGPUMLSchedStrategy::initialize(ScheduleDAGMI *DAG) { | ||
| // ML scheduling strategy is only done top-down to support new resource | ||
| // balancing heuristics. | ||
| RegionPolicy.OnlyTopDown = true; | ||
| RegionPolicy.OnlyBottomUp = false; | ||
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| GCNSchedStrategy::initialize(DAG); | ||
| } | ||
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| bool AMDGPUMLSchedStrategy::tryCandidate(SchedCandidate &Cand, | ||
| SchedCandidate &TryCand, | ||
| SchedBoundary *Zone) const { | ||
| // Initialize the candidate if needed. | ||
| if (!Cand.isValid()) { | ||
| TryCand.Reason = FirstValid; | ||
| return true; | ||
| } | ||
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| // Bias PhysReg Defs and copies to their uses and defined respectively. | ||
| if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop), | ||
| biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg)) | ||
| return TryCand.Reason != NoCand; | ||
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| // Avoid exceeding the target's limit. | ||
| if (DAG->isTrackingPressure() && | ||
| tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand, | ||
| RegExcess, TRI, DAG->MF)) | ||
| return TryCand.Reason != NoCand; | ||
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| // We only compare a subset of features when comparing nodes between | ||
| // Top and Bottom boundary. Some properties are simply incomparable, in many | ||
| // other instances we should only override the other boundary if something | ||
| // is a clear good pick on one boundary. Skip heuristics that are more | ||
| // "tie-breaking" in nature. | ||
| bool SameBoundary = Zone != nullptr; | ||
| if (SameBoundary) { | ||
| // For loops that are acyclic path limited, aggressively schedule for | ||
| // latency. Within an single cycle, whenever CurrMOps > 0, allow normal | ||
| // heuristics to take precedence. | ||
| if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() && | ||
| tryLatency(TryCand, Cand, *Zone)) | ||
| return TryCand.Reason != NoCand; | ||
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| // Prioritize instructions that read unbuffered resources by stall cycles. | ||
| if (tryLess(Zone->getLatencyStallCycles(TryCand.SU), | ||
| Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) | ||
| return TryCand.Reason != NoCand; | ||
| } | ||
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| // Keep clustered nodes together to encourage downstream peephole | ||
| // optimizations which may reduce resource requirements. | ||
| // | ||
| // This is a best effort to set things up for a post-RA pass. Optimizations | ||
| // like generating loads of multiple registers should ideally be done within | ||
| // the scheduler pass by combining the loads during DAG postprocessing. | ||
| unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID; | ||
| unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID; | ||
| bool CandIsClusterSucc = | ||
| isTheSameCluster(CandZoneCluster, Cand.SU->ParentClusterIdx); | ||
| bool TryCandIsClusterSucc = | ||
| isTheSameCluster(TryCandZoneCluster, TryCand.SU->ParentClusterIdx); | ||
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| if (tryGreater(TryCandIsClusterSucc, CandIsClusterSucc, TryCand, Cand, | ||
| Cluster)) | ||
| return TryCand.Reason != NoCand; | ||
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| if (SameBoundary) { | ||
| // Weak edges are for clustering and other constraints. | ||
| if (tryLess(getWeakLeft(TryCand.SU, TryCand.AtTop), | ||
| getWeakLeft(Cand.SU, Cand.AtTop), TryCand, Cand, Weak)) | ||
| return TryCand.Reason != NoCand; | ||
| } | ||
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| // Avoid increasing the max pressure of the entire region. | ||
| if (DAG->isTrackingPressure() && | ||
| tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax, TryCand, | ||
| Cand, RegMax, TRI, DAG->MF)) | ||
| return TryCand.Reason != NoCand; | ||
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| if (SameBoundary) { | ||
| // Avoid critical resource consumption and balance the schedule. | ||
| TryCand.initResourceDelta(DAG, SchedModel); | ||
| if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources, | ||
| TryCand, Cand, ResourceReduce)) | ||
| return TryCand.Reason != NoCand; | ||
| if (tryGreater(TryCand.ResDelta.DemandedResources, | ||
| Cand.ResDelta.DemandedResources, TryCand, Cand, | ||
| ResourceDemand)) | ||
| return TryCand.Reason != NoCand; | ||
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| // Avoid serializing long latency dependence chains. | ||
| // For acyclic path limited loops, latency was already checked above. | ||
| if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency && | ||
| !Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, *Zone)) | ||
| return TryCand.Reason != NoCand; | ||
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| // Fall through to original instruction order. | ||
| if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) || | ||
| (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { | ||
| TryCand.Reason = NodeOrder; | ||
| return true; | ||
| } | ||
| } | ||
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| return false; | ||
| } | ||
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| AMDGPUMLPostSchedStrategy::AMDGPUMLPostSchedStrategy( | ||
| const MachineSchedContext *C) | ||
| : PostGenericScheduler(C) {} | ||
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| bool AMDGPUMLPostSchedStrategy::tryCandidate(SchedCandidate &Cand, | ||
| SchedCandidate &TryCand) { | ||
| // Initialize the candidate if needed. | ||
| if (!Cand.isValid()) { | ||
| TryCand.Reason = FirstValid; | ||
| return true; | ||
| } | ||
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| // Fall through to original instruction order. | ||
| // This effectively only enables hazard checking for post-RA scheduling. | ||
| if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { | ||
| TryCand.Reason = NodeOrder; | ||
| return true; | ||
| } | ||
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| return false; | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,43 @@ | ||
| //===-- AMDGPUMLSchedStrategy.h - ML-focused Scheduler Strategy -*- C++ -*-===// | ||
| // | ||
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| // | ||
| /// \file | ||
| /// ML-focused scheduling strategy for AMDGPU. | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
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| #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMLSCHEDSTRATEGY_H | ||
| #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMLSCHEDSTRATEGY_H | ||
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| #include "GCNSchedStrategy.h" | ||
| #include "llvm/CodeGen/MachineScheduler.h" | ||
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| namespace llvm { | ||
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| class AMDGPUMLSchedStrategy final : public GCNSchedStrategy { | ||
| protected: | ||
| bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, | ||
| SchedBoundary *Zone) const override; | ||
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| public: | ||
| AMDGPUMLSchedStrategy(const MachineSchedContext *C); | ||
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| void initialize(ScheduleDAGMI *DAG) override; | ||
| }; | ||
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| class AMDGPUMLPostSchedStrategy : public PostGenericScheduler { | ||
| protected: | ||
| bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override; | ||
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| public: | ||
| AMDGPUMLPostSchedStrategy(const MachineSchedContext *C); | ||
| }; | ||
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| } // End namespace llvm | ||
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| #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMLSCHEDSTRATEGY_H | ||
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missing empty line at EoF