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[RISCV] LMUL lists for indexed and strided loads #169756

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Merged
ppenzin merged 3 commits into from
Dec 5, 2025
Merged

[RISCV] LMUL lists for indexed and strided loads #169756

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7d85a03
[RISCV] LMUL lists for indexed and strided loads
ppenzin Nov 27, 2025
ee50e3d
DS -> SX in MxLists aliases
ppenzin Dec 2, 2025
8760ed4
Use EEW in MxList aliases
ppenzin Dec 4, 2025
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12 changes: 5 additions & 7 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Original file line number Diff line number Diff line change
Expand Up @@ -562,7 +562,7 @@ multiclass SiFive7WriteResBase<int VLEN,
// resource, we do not need to use LMULSEWXXX constructors. However, we do
// use the SEW from the name to determine the number of Cycles.

foreach mx = SchedMxList in {
foreach mx = SchedMxListDS8 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
Expand All @@ -582,10 +582,8 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX8", [VCQ, VS], mx, IsWorstCase>;
}
}
// TODO: The MxLists need to be filtered by EEW. We only need to support
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@wangpc-pp wangpc-pp Nov 27, 2025

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Do we need to keep this TODO?

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@ppenzin ppenzin Nov 28, 2025 •
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I can revert that. If we try to implement this we would need to create a macro that takes EEW and returns a MxList, and this change doesn't quite get there. @mshockwave any objections on keeping the TODO?

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@mshockwave mshockwave Nov 30, 2025

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I think this comment might be outdated already: the fact that it excludes MF8 means that it already accounts for EEW, as explained by the comment itself.

// LMUL >= SEW_min/ELEN. Here, the smallest EEW prevents us from having MF8
// since LMUL >= 16/64.
foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {

foreach mx = SchedMxListDS16 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
Expand All @@ -605,7 +603,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX16", [VCQ, VS], mx, IsWorstCase>;
}
}
foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
foreach mx = SchedMxListDS32 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
Expand All @@ -625,7 +623,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX32", [VCQ, VS], mx, IsWorstCase>;
}
}
foreach mx = ["M1", "M2", "M4", "M8"] in {
foreach mx = SchedMxListDS64 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
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Original file line number Diff line number Diff line change
Expand Up @@ -437,7 +437,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}

foreach mx = SchedMxList in {
foreach mx = SchedMxListDS8 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
Expand All @@ -449,7 +449,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
}
}
foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
foreach mx = SchedMxListDS16 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
Expand All @@ -461,7 +461,7 @@ foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
}
}
foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
foreach mx = SchedMxListDS32 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
Expand All @@ -473,7 +473,7 @@ foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
}
}
foreach mx = ["M1", "M2", "M4", "M8"] in {
foreach mx = SchedMxListDS64 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVScheduleV.td
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Expand Up @@ -19,6 +19,14 @@ defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
// Used for widening floating-point Reduction as it doesn't contain MF8.
defvar SchedMxListFWRed = SchedMxListF;
// Used for indexed and strided loads of 8 bit lanes, same as full MX list
defvar SchedMxListDS8 = SchedMxList;
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@mshockwave mshockwave Nov 30, 2025

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is there any reason the suffix is called "DS"? Is it coming from SchedWrite names like "WriteVLDS8"? I believe those names should be read as: "V" + "LD" (load) + "S" (strided) + "8" (EEW).

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@ppenzin ppenzin Dec 2, 2025

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Focused on wrong common letter, sorry

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@ppenzin ppenzin Dec 2, 2025

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Updated the aliases. Is SX (for S and UX/OX) better?

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@topperc topperc Dec 2, 2025

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This is just a list of allowed MX values for a particular EEW. It doesn't need to mention strided or indexed at all. Maybe SchedMxListEEW8, SchedMxListEEW16, SchedMxListEEW32, SchedMxListEEW64?

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@mshockwave mshockwave Dec 3, 2025

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second that names like SchedMxListEEW8 might be more general.

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@ppenzin ppenzin Dec 4, 2025

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Addressed.

// Used for indexed and strided loads of 16 bit lanes
defvar SchedMxListDS16 = SchedMxListF;
// Used for indexed and strided loads of 32 bit lanes
defvar SchedMxListDS32 = !listremove(SchedMxListDS16, ["MF4"]);
// Used for indexed and strided loads of 64 bit lanes
defvar SchedMxListDS64 = !listremove(SchedMxListDS32, ["MF2"]);

class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
Expand Down