Skip to content

[AArch64][SVE] Add SubtargetFeature to disable lowering unpredicated loads/stores as… #170256

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
kinoshita-fj wants to merge 1 commit into
base: main
Choose a base branch
from
+38 −2
Open

[AArch64][SVE] Add SubtargetFeature to disable lowering unpredicated loads/stores as… #170256

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Features.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -915,6 +915,10 @@ def FeatureUseWzrToVecMove : SubtargetFeature<"use-wzr-to-vec-move",
"UseWzrToVecMove", "true",
"Move from WZR to insert 0 into vector registers">;

def FeatureDisableUnpredicatedLdStLower : SubtargetFeature<
"disable-unpredicated-ld-st-lower", "DisableUnpredicatedLdStLower",
"true", "Disable lowering unpredicated loads/stores as LDR/STR">;

//===----------------------------------------------------------------------===//
// Architectures.
//
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -443,6 +443,8 @@ def AllowMisalignedMemAccesses

def UseWzrToVecMove : Predicate<"Subtarget->useWzrToVecMove()">;

def AllowUnpredicatedLdStLower
Copy link
Collaborator

@paulwalker-arm paulwalker-arm Dec 2, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Up to you but perhaps "AggressiveUseOfSVEFillSpillInstructions" and "DisableAggressiveUseOfSVEFillSpillInstructions"?

: Predicate<"!Subtarget->disableUnpredicatedLdStLower()">;

//===----------------------------------------------------------------------===//
// AArch64-specific DAG Nodes.
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64Processors.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -306,7 +306,8 @@ def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
FeatureAggressiveFMA,
FeatureArithmeticBccFusion,
FeatureStorePairSuppress,
FeaturePredictableSelectIsExpensive]>;
FeaturePredictableSelectIsExpensive,
FeatureDisableUnpredicatedLdStLower]>;

def TuneMONAKA : SubtargetFeature<"fujitsu-monaka", "ARMProcFamily", "MONAKA",
"Fujitsu FUJITSU-MONAKA processors", [
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3164,7 +3164,7 @@ let Predicates = [HasSVE_or_SME] in {
}

// Allow using LDR/STR to avoid the predicate dependence.
let Predicates = [HasSVE_or_SME, IsLE, AllowMisalignedMemAccesses] in
let Predicates = [HasSVE_or_SME, IsLE, AllowMisalignedMemAccesses, AllowUnpredicatedLdStLower] in
foreach Ty = [ nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv8f16, nxv4f32, nxv2f64, nxv8bf16 ] in {
let AddedComplexity = 2 in {
def : Pat<(Ty (load (am_sve_indexed_s9 GPR64sp:$base, simm9:$offset))),
Expand Down
29 changes: 29 additions & 0 deletions llvm/test/CodeGen/AArch64/sve-disable-unpredicated-load-store-lower.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+disable-unpredicated-ld-st-lower < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck --check-prefix CHECK-DEFAULT %s
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=a64fx < %s | FileCheck --check-prefix CHECK-A64FX %s

Comment on lines +1 to +5
Copy link
Collaborator

@paulwalker-arm paulwalker-arm Dec 2, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

To increase the test coverage, rather than adding a new file, please can you add the extra RUN lines to llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll and llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll instead?

define void @nxv2i64(ptr %ldptr, ptr %stptr) {
; CHECK-LABEL: nxv2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret
;
; CHECK-DEFAULT-LABEL: nxv2i64:
; CHECK-DEFAULT: // %bb.0:
; CHECK-DEFAULT-NEXT: ldr z0, [x0]
; CHECK-DEFAULT-NEXT: str z0, [x1]
; CHECK-DEFAULT-NEXT: ret
;
; CHECK-A64FX-LABEL: nxv2i64:
; CHECK-A64FX: // %bb.0:
; CHECK-A64FX-NEXT: ptrue p0.d
; CHECK-A64FX-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-A64FX-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-A64FX-NEXT: ret
%l3 = load <vscale x 2 x i64>, ptr %ldptr, align 8
store <vscale x 2 x i64> %l3, ptr %stptr, align 8
ret void
}
Loading