[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR#170335

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tlinthic wants to merge 17 commits intollvm:mainfrom

tlinthic:RewriteScheduleStage

Commits on Dec 8, 2025

[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR

jrbyrnes
authored and
Tony Linthicum
committed
Do not rewrite to AGPR if waves-per-eu >= 2

jrbyrnes
authored and
Tony Linthicum
committed
Review comments

jrbyrnes
authored and
Tony Linthicum
committed
merge of PR 149367
Tony Linthicum
committed
Address PR 149367 review comments
Tony Linthicum
committed
Address PR 149367 review comments
Tony Linthicum
committed
[AMDGPU] Add scheduling stage to rewrite MFMA from VGPR to AGPR
Tony Linthicum
committed
Remove unnecessary second hasFFX90AInsts conditional check
Tony Linthicum
committed
Format fixes from review comments.
Tony Linthicum
committed
Use VNInfo api to check for PHI def rather than doing it manually
Tony Linthicum
committed
Review comments
Tony Linthicum
committed
Review comments
Tony Linthicum
committed

Commits on Dec 9, 2025

review comments: make MachineScheduler require MachineBlockFrequencyInfo and
Tony Linthicum
committed
Review comments
Tony Linthicum
committed
Review comments: add MachineBlockFrequencyAnalysis as preserved to PHI elimination,
Tony Linthicum
committed
Review comments: only reset instruction descriptor when the rewrite is actually going
Tony Linthicum
committed
Review comments: remove map lookup inside loop
Tony Linthicum
committed