Skip to content

AMDGPU: Generalize and normalize some tests to avoid future churn #170508

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
nhaehnle merged 1 commit into from
Dec 3, 2025
Merged

AMDGPU: Generalize and normalize some tests to avoid future churn #170508

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AMDGPU/vector-alloca-atomic.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,19 +1,19 @@
; RUN: opt -S -mtriple=amdgcn-- -data-layout=A5 -passes='amdgpu-promote-alloca,sroa,instcombine' < %s | FileCheck -check-prefix=OPT %s
; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-promote-alloca,sroa,instcombine' < %s | FileCheck -check-prefix=OPT %s

; Show that what the alloca promotion pass will do for non-atomic load/store.

; OPT-LABEL: @vector_alloca_not_atomic(
;
; OPT: extractelement <3 x i32> <i32 0, i32 1, i32 2>, i64 %index
define amdgpu_kernel void @vector_alloca_not_atomic(ptr addrspace(1) %out, i64 %index) {
; OPT: extractelement <3 x i32> <i32 0, i32 1, i32 2>, i32 %index
define amdgpu_kernel void @vector_alloca_not_atomic(ptr addrspace(1) %out, i32 %index) {
entry:
%alloca = alloca [3 x i32], addrspace(5)
%a1 = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 1
%a2 = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 2
store i32 0, ptr addrspace(5) %alloca
store i32 1, ptr addrspace(5) %a1
store i32 2, ptr addrspace(5) %a2
%tmp = getelementptr [3 x i32], ptr addrspace(5) %alloca, i64 0, i64 %index
%tmp = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 %index
%data = load i32, ptr addrspace(5) %tmp
store i32 %data, ptr addrspace(1) %out
ret void
Expand All @@ -26,15 +26,15 @@ entry:
; OPT: store i32 1, ptr addrspace(5)
; OPT: store i32 2, ptr addrspace(5)
; OPT: load atomic i32, ptr addrspace(5)
define amdgpu_kernel void @vector_alloca_atomic_read(ptr addrspace(1) %out, i64 %index) {
define amdgpu_kernel void @vector_alloca_atomic_read(ptr addrspace(1) %out, i32 %index) {
entry:
%alloca = alloca [3 x i32], addrspace(5)
%a1 = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 1
%a2 = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 2
store i32 0, ptr addrspace(5) %alloca
store i32 1, ptr addrspace(5) %a1
store i32 2, ptr addrspace(5) %a2
%tmp = getelementptr [3 x i32], ptr addrspace(5) %alloca, i64 0, i64 %index
%tmp = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 %index
%data = load atomic i32, ptr addrspace(5) %tmp acquire, align 4
store i32 %data, ptr addrspace(1) %out
ret void
Expand All @@ -47,15 +47,15 @@ entry:
; OPT: store atomic i32 1, ptr addrspace(5)
; OPT: store atomic i32 2, ptr addrspace(5)
; OPT: load i32, ptr addrspace(5)
define amdgpu_kernel void @vector_alloca_atomic_write(ptr addrspace(1) %out, i64 %index) {
define amdgpu_kernel void @vector_alloca_atomic_write(ptr addrspace(1) %out, i32 %index) {
entry:
%alloca = alloca [3 x i32], addrspace(5)
%a1 = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 1
%a2 = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 2
store atomic i32 0, ptr addrspace(5) %alloca release, align 4
store atomic i32 1, ptr addrspace(5) %a1 release, align 4
store atomic i32 2, ptr addrspace(5) %a2 release, align 4
%tmp = getelementptr [3 x i32], ptr addrspace(5) %alloca, i64 0, i64 %index
%tmp = getelementptr [3 x i32], ptr addrspace(5) %alloca, i32 0, i32 %index
%data = load i32, ptr addrspace(5) %tmp
store i32 %data, ptr addrspace(1) %out
ret void
Expand Down
6 changes: 4 additions & 2 deletions llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,8 @@ entry:
; OPT-NOT: alloca
; OPT: bb2:
; OPT: %promotealloca = phi <6 x float> [ zeroinitializer, %bb ], [ %0, %bb2 ]
; OPT: %0 = insertelement <6 x float> %promotealloca, float %tmp71, i32 %tmp10
; OPT: [[TMP:%tmp7.*]] = load float, ptr addrspace(1) %tmp5, align 4
; OPT: %0 = insertelement <6 x float> %promotealloca, float [[TMP]], i32 %tmp10
; OPT: .preheader:
; OPT: %bc = bitcast <6 x float> %0 to <6 x i32>
; OPT: %1 = extractelement <6 x i32> %bc, i32 %tmp20
Expand Down Expand Up @@ -132,7 +133,8 @@ bb15: ; preds = %.preheader
; OPT-NOT: alloca
; OPT: bb2:
; OPT: %promotealloca = phi <6 x double> [ zeroinitializer, %bb ], [ %0, %bb2 ]
; OPT: %0 = insertelement <6 x double> %promotealloca, double %tmp71, i32 %tmp10
; OPT: [[TMP:%tmp7.*]] = load double, ptr addrspace(1) %tmp5, align 8
; OPT: %0 = insertelement <6 x double> %promotealloca, double [[TMP]], i32 %tmp10
; OPT: .preheader:
; OPT: %bc = bitcast <6 x double> %0 to <6 x i64>
; OPT: %1 = extractelement <6 x i64> %bc, i32 %tmp20
Expand Down
Loading