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11 changes: 11 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5808,6 +5808,17 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}

if (ST.hasFlatScratchHiInB64InstHazard() && isSALU(MI) &&
MI.readsRegister(AMDGPU::SRC_FLAT_SCRATCH_BASE_HI, nullptr)) {
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nullptr here is intentional, I do not mean to include 64-bit SRC_FLAT_SCRATCH_BASE.

const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst);
if ((Dst && RI.getRegClassForReg(MRI, Dst->getReg()) ==
&AMDGPU::SReg_64RegClass) ||
Opcode == AMDGPU::S_BITCMP0_B64 || Opcode == AMDGPU::S_BITCMP1_B64) {
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Why are these opcodes special cased?

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These do not have sdst but listed as hazard in the ticket.

ErrInfo = "Instruction cannot read flat_scratch_base_hi";
return false;
}
}

return true;
}

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66 changes: 66 additions & 0 deletions llvm/test/MachineVerifier/AMDGPU/hazard-gfx1250-flat-src-hi.mir
Original file line number Diff line number Diff line change
@@ -0,0 +1,66 @@
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s

---
name: salu_64_bit_inst_reads_flat_scratch_base_hi
tracksRegLiveness: true
body: |
bb.0:

%0:sreg_64 = IMPLICIT_DEF
$sgpr0_sgpr1 = IMPLICIT_DEF

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_ASHR_I64

%1:sreg_64 = S_ASHR_I64 %0:sreg_64, $src_flat_scratch_base_hi, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_LSHL_B64

%2:sreg_64 = S_LSHL_B64 %0:sreg_64, $src_flat_scratch_base_hi, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_LSHR_B64

%3:sreg_64 = S_LSHR_B64 %0:sreg_64, $src_flat_scratch_base_hi, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BFE_I64

%4:sreg_64 = S_BFE_I64 %0:sreg_64, $src_flat_scratch_base_hi, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BFE_U64

%5:sreg_64 = S_BFE_U64 %0:sreg_64, $src_flat_scratch_base_hi, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BFM_B64

%6:sreg_64 = S_BFM_B64 $src_flat_scratch_base_hi, 1, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BITCMP0_B64

S_BITCMP0_B64 %0:sreg_64, $src_flat_scratch_base_hi, implicit $scc, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BITCMP1_B64

S_BITCMP1_B64 %0:sreg_64, $src_flat_scratch_base_hi, implicit $scc, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BITREPLICATE_B64_B32

%7:sreg_64 = S_BITREPLICATE_B64_B32 $src_flat_scratch_base_hi, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BITSET0_B64

$sgpr0_sgpr1 = S_BITSET0_B64 $src_flat_scratch_base_hi, $sgpr0_sgpr1, implicit-def $scc

; CHECK: *** Bad machine code: Instruction cannot read flat_scratch_base_hi ***
; CHECK: S_BITSET1_B64

$sgpr0_sgpr1 = S_BITSET1_B64 $src_flat_scratch_base_hi, $sgpr0_sgpr1, implicit-def $scc
...
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