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[RISCV] Make RISCVInstrInfo::verifyInstruction stricter for immediate-only operands #170736

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Merged
topperc merged 4 commits into from
Dec 4, 2025
Merged

[RISCV] Make RISCVInstrInfo::verifyInstruction stricter for immediate-only operands #170736

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fd39725
[RISCV] Make RISCVInstrInfo::verifyInstruction stricter for immediate…
topperc Dec 4, 2025
814a036
Merge branch 'main' into pr/verify-immediate
topperc Dec 4, 2025
c2b3201
fixup! Fix llvm-exegesis
topperc Dec 4, 2025
b242961
fixup! More llvm-exegesis
topperc Dec 4, 2025
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12 changes: 9 additions & 3 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -393,7 +393,6 @@ enum OperandType : unsigned {
OPERAND_UIMM14_LSB00,
OPERAND_UIMM16,
OPERAND_UIMM16_NONZERO,
OPERAND_UIMM20,
OPERAND_UIMMLOG2XLEN,
OPERAND_UIMMLOG2XLEN_NONZERO,
OPERAND_UIMM32,
Expand All @@ -412,13 +411,11 @@ enum OperandType : unsigned {
OPERAND_SIMM10_LSB0000_NONZERO,
OPERAND_SIMM10_UNSIGNED,
OPERAND_SIMM11,
OPERAND_SIMM12,
OPERAND_SIMM12_LSB00000,
OPERAND_SIMM16,
OPERAND_SIMM16_NONZERO,
OPERAND_SIMM20_LI,
OPERAND_SIMM26,
OPERAND_BARE_SIMM32,
OPERAND_CLUI_IMM,
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
Expand Down Expand Up @@ -447,6 +444,15 @@ enum OperandType : unsigned {
// Vtype operand for XSfmm extension.
OPERAND_XSFMM_VTYPE,
OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_VTYPE,

OPERAND_UIMM20_LUI,
OPERAND_UIMM20_AUIPC,

// Simm12 or constant pool, global, basicblock, etc.
OPERAND_SIMM12_LO,

OPERAND_BARE_SIMM32,

// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
Expand Down
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