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[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes #171446

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[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes #171446

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a4d6748
[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes
Lukacma Dec 9, 2025
52d800a
Merge branch 'main' into cvt-round-gi
Lukacma Dec 9, 2025
576e93c
Fix vector-lrint test
Lukacma Dec 9, 2025
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46 changes: 46 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6841,6 +6841,29 @@ defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "F
defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;

// For global-isel we can use register classes to determine
// which FCVT instruction to use.
let Predicates = [HasFPRCVT] in {
def : Pat<(i32 (lround f16:$Rn)),
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@davemgreen davemgreen Dec 9, 2025

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I'm not sure if this file is very consistent, but the patterns below are indented and these are not. We could do with being consistent in the same instructions at least. (I think I would go with no indentation for Predicates).

(FCVTASSHr f16:$Rn)>;
def : Pat<(i32 (lround f64:$Rn)),
(FCVTASSDr f64:$Rn)>;
def : Pat<(i64 (lround f16:$Rn)),
(FCVTASDHr f16:$Rn)>;
def : Pat<(i64 (llround f16:$Rn)),
(FCVTASDHr f16:$Rn)>;
def : Pat<(i64 (lround f32:$Rn)),
(FCVTASDSr f32:$Rn)>;
def : Pat<(i64 (llround f32:$Rn)),
(FCVTASDSr f32:$Rn)>;
}
def : Pat<(i32 (lround f32:$Rn)),
(FCVTASv1i32 f32:$Rn)>;
def : Pat<(i64 (lround f64:$Rn)),
(FCVTASv1i64 f64:$Rn)>;
def : Pat<(i64 (llround f64:$Rn)),
(FCVTASv1i64 f64:$Rn)>;

let Predicates = [HasFPRCVT] in {
def : Pat<(f32 (bitconvert (i32 (any_lround f16:$Rn)))),
(FCVTASSHr f16:$Rn)>;
Expand All @@ -6862,6 +6885,29 @@ def : Pat<(f64 (bitconvert (i64 (any_lround f64:$Rn)))),
def : Pat<(f64 (bitconvert (i64 (any_llround f64:$Rn)))),
(FCVTASv1i64 f64:$Rn)>;

// For global-isel we can use register classes to determine
// which FCVT instruction to use.
let Predicates = [HasFPRCVT] in {
def : Pat<(i32 (lrint f16:$Rn)),
(FCVTZSSHr (FRINTXHr f16:$Rn))>;
def : Pat<(i32 (lrint f64:$Rn)),
(FCVTZSSDr (FRINTXDr f64:$Rn))>;
def : Pat<(i64 (lrint f16:$Rn)),
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
def : Pat<(i64 (llrint f16:$Rn)),
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
def : Pat<(i64 (lrint f32:$Rn)),
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
def : Pat<(i64 (llrint f32:$Rn)),
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
}
def : Pat<(i32 (lrint f32:$Rn)),
(FCVTZSv1i32 (FRINTXSr f32:$Rn))>;
def : Pat<(i64 (lrint f64:$Rn)),
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;
def : Pat<(i64 (llrint f64:$Rn)),
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;

let Predicates = [HasFPRCVT] in {
def : Pat<(f32 (bitconvert (i32 (any_lrint f16:$Rn)))),
(FCVTZSSHr (FRINTXHr f16:$Rn))>;
Expand Down
18 changes: 5 additions & 13 deletions llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -867,7 +867,11 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FPTOSI_SAT:
case TargetOpcode::G_FPTOUI_SAT:
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: {
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_INTRINSIC_LRINT:
case TargetOpcode::G_INTRINSIC_LLRINT:
case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND: {
LLT DstType = MRI.getType(MI.getOperand(0).getReg());
if (DstType.isVector())
break;
Expand All @@ -888,12 +892,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
}
case TargetOpcode::G_INTRINSIC_LRINT:
case TargetOpcode::G_INTRINSIC_LLRINT:
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
break;
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
case TargetOpcode::G_FCMP: {
// If the result is a vector, it must use a FPR.
AArch64GenRegisterBankInfo::PartialMappingIdx Idx0 =
Expand Down Expand Up @@ -1233,12 +1231,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
break;
}
case TargetOpcode::G_LROUND:
case TargetOpcode::G_LLROUND: {
// Source is always floating point and destination is always integer.
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
}
}

// Finally construct the computed mapping.
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
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Expand Up @@ -14,7 +14,7 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
; CHECK-NEXT: %llround:gpr(s64) = G_LLROUND %fpr(s64)
; CHECK-NEXT: %llround:fpr(s64) = G_LLROUND %fpr(s64)
; CHECK-NEXT: $d0 = COPY %llround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%fpr:_(s64) = COPY $d0
Expand All @@ -35,7 +35,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x0
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
; CHECK-NEXT: %llround:gpr(s64) = G_LLROUND [[COPY]](s64)
; CHECK-NEXT: %llround:fpr(s64) = G_LLROUND [[COPY]](s64)
; CHECK-NEXT: $d0 = COPY %llround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
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Expand Up @@ -14,7 +14,7 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
; CHECK-NEXT: %lround:gpr(s64) = G_LROUND %fpr(s64)
; CHECK-NEXT: %lround:fpr(s64) = G_LROUND %fpr(s64)
; CHECK-NEXT: $d0 = COPY %lround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%fpr:_(s64) = COPY $d0
Expand All @@ -35,7 +35,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x0
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
; CHECK-NEXT: %lround:gpr(s64) = G_LROUND [[COPY]](s64)
; CHECK-NEXT: %lround:fpr(s64) = G_LROUND [[COPY]](s64)
; CHECK-NEXT: $d0 = COPY %lround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-cvt-simd-round-rint.ll
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@@ -1,6 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT


;
; Lround
Expand Down
42 changes: 27 additions & 15 deletions llvm/test/CodeGen/AArch64/vector-lrint.ll
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Expand Up @@ -56,13 +56,13 @@


define <1 x iXLen> @lrint_v1f16(<1 x half> %x) nounwind {
; CHECK-i32-LABEL: lrint_v1f16:
; CHECK-i32: // %bb.0:
; CHECK-i32-NEXT: fcvt s0, h0
; CHECK-i32-NEXT: frintx s0, s0
; CHECK-i32-NEXT: fcvtzs w8, s0
; CHECK-i32-NEXT: fmov s0, w8
; CHECK-i32-NEXT: ret
; CHECK-i32-SD-LABEL: lrint_v1f16:
; CHECK-i32-SD: // %bb.0:
; CHECK-i32-SD-NEXT: fcvt s0, h0
; CHECK-i32-SD-NEXT: frintx s0, s0
; CHECK-i32-SD-NEXT: fcvtzs w8, s0
; CHECK-i32-SD-NEXT: fmov s0, w8
; CHECK-i32-SD-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v1f16:
; CHECK-i64: // %bb.0:
Expand All @@ -71,6 +71,13 @@ define <1 x iXLen> @lrint_v1f16(<1 x half> %x) nounwind {
; CHECK-i64-NEXT: fcvtzs x8, s0
; CHECK-i64-NEXT: fmov d0, x8
; CHECK-i64-NEXT: ret
;
; CHECK-i32-GI-LABEL: lrint_v1f16:
; CHECK-i32-GI: // %bb.0:
; CHECK-i32-GI-NEXT: fcvt s0, h0
; CHECK-i32-GI-NEXT: frintx s0, s0
; CHECK-i32-GI-NEXT: fcvtzs s0, s0
; CHECK-i32-GI-NEXT: ret
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x)
ret <1 x iXLen> %a
}
Expand Down Expand Up @@ -776,8 +783,7 @@ define <1 x iXLen> @lrint_v1f32(<1 x float> %x) nounwind {
; CHECK-i32-GI-LABEL: lrint_v1f32:
; CHECK-i32-GI: // %bb.0:
; CHECK-i32-GI-NEXT: frintx s0, s0
; CHECK-i32-GI-NEXT: fcvtzs w8, s0
; CHECK-i32-GI-NEXT: fmov s0, w8
; CHECK-i32-GI-NEXT: fcvtzs s0, s0
; CHECK-i32-GI-NEXT: ret
;
; CHECK-i64-GI-LABEL: lrint_v1f32:
Expand Down Expand Up @@ -1012,12 +1018,18 @@ define <1 x iXLen> @lrint_v1f64(<1 x double> %x) nounwind {
; CHECK-i32-NEXT: fmov s0, w8
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v1f64:
; CHECK-i64: // %bb.0:
; CHECK-i64-NEXT: frintx d0, d0
; CHECK-i64-NEXT: fcvtzs x8, d0
; CHECK-i64-NEXT: fmov d0, x8
; CHECK-i64-NEXT: ret
; CHECK-i64-SD-LABEL: lrint_v1f64:
; CHECK-i64-SD: // %bb.0:
; CHECK-i64-SD-NEXT: frintx d0, d0
; CHECK-i64-SD-NEXT: fcvtzs x8, d0
; CHECK-i64-SD-NEXT: fmov d0, x8
; CHECK-i64-SD-NEXT: ret
;
; CHECK-i64-GI-LABEL: lrint_v1f64:
; CHECK-i64-GI: // %bb.0:
; CHECK-i64-GI-NEXT: frintx d0, d0
; CHECK-i64-GI-NEXT: fcvtzs d0, d0
; CHECK-i64-GI-NEXT: ret
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double> %x)
ret <1 x iXLen> %a
}
Expand Down