[RISCV] Make MOP/HINT-based instruction mnemonics always available

llvm/docs/ReleaseNotes.md

@@ -125,6 +125,10 @@ Changes to the RISC-V Backend
 * `llvm-objdump` now has support for `--symbolize-operands` with RISC-V.
 * `-mcpu=spacemit-x100` was added.
 * Change P extension version to match the 019 draft specification. Encoded in `-march` as `0p19`.
+* Mnemonics for MOP/HINT-based instructions (`lpad`, `pause`, `ntl.*`, `c.ntl.*`,
+  `sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always
+  available in the assembler and disassembler without requiring their respective
+  extensions.
 
 Changes to the WebAssembly Backend
 ----------------------------------

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -1115,7 +1115,8 @@ def : InstAlias<"jalr $rd, (${rs})",      (JALR GPR:$rd, GPR:$rs, 0), 0>;
 
 def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
 
-let Predicates = [HasStdExtZihintpause] in
+// pause is always available in the assembler and disassembler, even without
+// enabling Zihintpause, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474).
 def : InstAlias<"pause", (FENCE 0x1, 0x0)>; // 0x1 == w
 
 def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0), 2>;
@@ -1156,12 +1157,13 @@ def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
 def : InstAlias<"hfence.vvma",     (HFENCE_VVMA      X0, X0), 2>;
 def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>;
 
-let Predicates = [HasStdExtZihintntl] in {
-  def : InstAlias<"ntl.p1",     (ADD   X0, X0, X2)>;
-  def : InstAlias<"ntl.pall",   (ADD   X0, X0, X3)>;
-  def : InstAlias<"ntl.s1",     (ADD   X0, X0, X4)>;
-  def : InstAlias<"ntl.all",    (ADD   X0, X0, X5)>;
-} // Predicates = [HasStdExtZihintntl]
+// ntl.* hints are always available in the assembler and disassembler, even
+// without enabling Zihintntl, per psABI decision
+// (riscv-non-isa/riscv-elf-psabi-doc#474).
+def : InstAlias<"ntl.p1",     (ADD   X0, X0, X2)>;
+def : InstAlias<"ntl.pall",   (ADD   X0, X0, X3)>;
+def : InstAlias<"ntl.s1",     (ADD   X0, X0, X4)>;
+def : InstAlias<"ntl.all",    (ADD   X0, X0, X5)>;
 
 let EmitPriority = 0 in {
 def : InstAlias<"lb $rd, (${rs1})",
@@ -1229,9 +1231,9 @@ def : MnemonicAlias<"sbreak", "ebreak">;
 
 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
 
-let Predicates = [HasStdExtZicfilp] in {
+// lpad is always available in the assembler and disassembler, even without
+// enabling Zicfilp, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474).
 def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
-}
 
 //===----------------------------------------------------------------------===//
 // .insn directive instructions

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

@@ -596,12 +596,14 @@ def : InstAlias<"c.srli64 $rs1", (C_SRLI GPRC:$rs1, 0), 0>;
 def : InstAlias<"c.srai64 $rs1", (C_SRAI GPRC:$rs1, 0), 0>;
 }
 
-let Predicates = [HasStdExtC, HasStdExtZihintntl] in {
+// c.ntl.* hints are always available when Zca is present, even without
+// enabling Zihintntl, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474).
+let Predicates = [HasStdExtZca] in {
 def : InstAlias<"c.ntl.p1", (C_ADD X0, X2)>;
 def : InstAlias<"c.ntl.pall", (C_ADD X0, X3)>;
 def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>;
 def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;
-} // Predicates = [HasStdExtC, HasStdExtZihintntl]
+} // Predicates = [HasStdExtZca]
 
 let EmitPriority = 0 in {
 let Predicates = [HasStdExtZca] in {

llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td

@@ -20,7 +20,9 @@ class CMOPInst<bits<3> imm3, string opcodestr>
   let Inst{12-11} = 0;
 }
 
-foreach n = [1, 3, 5, 7, 9, 11, 13, 15] in {
+// c.mop.1 and c.mop.5 are aliases for c.sspush and c.sspopchk respectively,
+// defined in RISCVInstrInfoZicfiss.td.
+foreach n = [3, 7, 9, 11, 13, 15] in {
   let Predicates = [HasStdExtZcmop] in
   def C_MOP_ # n : CMOPInst<!srl(n, 1), "c.mop." # n>, Sched<[]>;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

@@ -24,7 +24,10 @@ class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
 // Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZicfiss] in {
+// Zicfiss instructions that use Zimop encoding space are available when Zimop
+// is enabled, without requiring Zicfiss explicitly. Per psABI decision
+// (riscv-non-isa/riscv-elf-psabi-doc#474).
+let Predicates = [HasStdExtZimop] in {
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
                        "$rs1"> {
@@ -45,16 +48,19 @@ def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
   let rd = 0b00000;
   let rs1 = 0b00000;
 }
-} // Predicates = [HasStdExtZicfiss]
+} // Predicates = [HasStdExtZimop]
 
-let Predicates = [HasStdExtZicfiss, HasStdExtZcmop],
+// Compressed Zicfiss instructions use Zcmop encoding space and are available
+// when Zcmop is enabled, without requiring Zicfiss explicitly. Per psABI
+// decision (riscv-non-isa/riscv-elf-psabi-doc#474).
+let Predicates = [HasStdExtZcmop],
     DecoderNamespace = "Zicfiss" in {
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
 
 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
-} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
+} // Predicates = [HasStdExtZcmop]
 
 let Predicates = [HasStdExtZicfiss] in
 defm SSAMOSWAP_W  : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
@@ -74,14 +80,21 @@ def PseudoMOP_SSPOPCHK : Pseudo<(outs), (ins GPRX1X5:$rs1), []>,
 let Predicates = [HasStdExtZcmop] in {
 let Uses = [X1], hasSideEffects = 1, mayLoad = 0, mayStore = 1 in
 def PseudoMOP_C_SSPUSH : Pseudo<(outs), (ins), []>,
-    PseudoInstExpansion<(C_MOP_1)>;
+    PseudoInstExpansion<(C_SSPUSH X1)>;
 } // Predicates = [HasStdExtZcmop]
 
 //===----------------------------------------------------------------------===/
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in {
+let Predicates = [HasStdExtZcmop] in {
 def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
 def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
-} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
+} // Predicates = [HasStdExtZcmop]
+
+// c.mop.1 and c.mop.5 are aliases for c.sspush ra and c.sspopchk t0.
+// Use EmitPriority=0 so disassembler prints c.sspush/c.sspopchk.
+let Predicates = [HasStdExtZcmop], EmitPriority = 0 in {
+def : InstAlias<"c.mop.1", (C_SSPUSH X1)>;
+def : InstAlias<"c.mop.5", (C_SSPOPCHK X5)>;
+} // Predicates = [HasStdExtZcmop], EmitPriority = 0

llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt

@@ -204,7 +204,7 @@
 0x7D 0x70
 
 # BAD: invalid instruction encoding
-# MOP: c.mop.1
+# MOP: c.sspush ra
 0x81 0x60
 
 # GOOD: c.lui ra, 1
@@ -782,7 +782,7 @@
 0x7D 0x72
 
 # BAD: invalid instruction encoding
-# MOP: c.mop.5
+# MOP: c.sspopchk t0
 0x81 0x62
 
 # GOOD: c.lui t0, 1

llvm/test/MC/RISCV/compressed-zicfiss.s

@@ -9,45 +9,59 @@
 # RUN:     | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 #
+# Compressed Zicfiss instructions only require Zcmop (and Zimop for
+# uncompressed forms), not Zicfiss (riscv-non-isa/riscv-elf-psabi-doc#474).
+#
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcmop,+zimop -M no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmop,+zimop < %s \
+# RUN:     | llvm-objdump --mattr=+zcmop,+zimop -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zcmop,+zimop -M no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmop,+zimop < %s \
+# RUN:     | llvm-objdump --mattr=+zcmop,+zimop -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
 # RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 sspopchk x5
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 sspopchk t0
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 sspush x1
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations)
 sspush ra
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
 c.sspush x1
 
 # CHECK-ASM-AND-OBJ: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
 c.sspush ra
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
 c.sspopchk x5
 
 # CHECK-ASM-AND-OBJ: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations)
 c.sspopchk t0

llvm/test/MC/RISCV/invalid-instruction-spellcheck.s

@@ -11,8 +11,8 @@
 # which are valid for the current set of features
 
 ad x1, x1, x1
-# CHECK-RV32: did you mean: add, addi, and, andi, la
-# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, sd
+# CHECK-RV32: did you mean: add, addi, and, andi, la, lpad
+# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, lpad, sd
 # CHECK-NEXT: ad x1, x1, x1
 
 fl ft0, 0(sp)

llvm/test/MC/RISCV/rv32i-invalid.s

@@ -196,7 +196,6 @@ sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the followi
 clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}}
 clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}}
 bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}}
-pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}}
 
 # Using floating point registers when integer registers are expected
 addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction

llvm/test/MC/RISCV/rvzcmop-valid.s

@@ -1,42 +1,52 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+zcmop -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+zcmop -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmop < %s \
 # RUN:     | llvm-objdump --mattr=+zcmop -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck --check-prefix=CHECK-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmop < %s \
 # RUN:     | llvm-objdump --mattr=+zcmop -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck --check-prefix=CHECK-OBJ %s
 
-# CHECK-ASM-AND-OBJ: c.mop.1
+# c.mop.1 is an alias for c.sspush ra.
+# CHECK-OBJ: c.sspush ra
+# CHECK-ASM: c.sspush ra
 # CHECK-ASM: encoding: [0x81,0x60]
 c.mop.1
 
-# CHECK-ASM-AND-OBJ: c.mop.3
+# CHECK-OBJ: c.mop.3
+# CHECK-ASM: c.mop.3
 # CHECK-ASM: encoding: [0x81,0x61]
 c.mop.3
 
-# CHECK-ASM-AND-OBJ: c.mop.5
+# c.mop.5 is an alias for c.sspopchk t0.
+# CHECK-OBJ: c.sspopchk t0
+# CHECK-ASM: c.sspopchk t0
 # CHECK-ASM: encoding: [0x81,0x62]
 c.mop.5
 
-# CHECK-ASM-AND-OBJ: c.mop.7
+# CHECK-OBJ: c.mop.7
+# CHECK-ASM: c.mop.7
 # CHECK-ASM: encoding: [0x81,0x63]
 c.mop.7
 
-# CHECK-ASM-AND-OBJ: c.mop.9
+# CHECK-OBJ: c.mop.9
+# CHECK-ASM: c.mop.9
 # CHECK-ASM: encoding: [0x81,0x64]
 c.mop.9
 
-# CHECK-ASM-AND-OBJ: c.mop.11
+# CHECK-OBJ: c.mop.11
+# CHECK-ASM: c.mop.11
 # CHECK-ASM: encoding: [0x81,0x65]
 c.mop.11
 
-# CHECK-ASM-AND-OBJ: c.mop.13
+# CHECK-OBJ: c.mop.13
+# CHECK-ASM: c.mop.13
 # CHECK-ASM: encoding: [0x81,0x66]
 c.mop.13
 
-# CHECK-ASM-AND-OBJ: c.mop.15
+# CHECK-OBJ: c.mop.15
+# CHECK-ASM: c.mop.15
 # CHECK-ASM: encoding: [0x81,0x67]
 c.mop.15

llvm/test/MC/RISCV/rvzihintntl-invalid.s

@@ -1,5 +1,11 @@
 # RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl < %s 2>&1 | FileCheck %s
 # RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl < %s 2>&1 | FileCheck %s
+#
+# ntl.* hints are always available even without Zihintntl
+# (riscv-non-isa/riscv-elf-psabi-doc#474).
+#
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
 
 ntl.p1 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.pall 2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
@@ -10,4 +16,3 @@ ntl.p1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.pall t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 ntl.s1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 ntl.all t0, t1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-

llvm/test/MC/RISCV/rvzihintntl-valid.s

@@ -8,6 +8,20 @@
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl < %s \
 # RUN:     | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# ntl.* hints are always available even without Zihintntl
+# (riscv-non-isa/riscv-elf-psabi-doc#474).
+#
+# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: add zero, zero, sp
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]

llvm/test/MC/RISCV/rvzihintntlc-valid.s

@@ -8,8 +8,25 @@
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
 # RUN:     | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+#
+# c.ntl.* hints are available when C extension is present, even without
+# enabling Zihintntl (riscv-non-isa/riscv-elf-psabi-doc#474).
+#
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
+# RUN:     | llvm-objdump --mattr=+c -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
+# RUN:     | llvm-objdump --mattr=+c -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# c.ntl.* still require the C extension.
+#
+# RUN: not llvm-mc %s -triple=riscv32 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]

llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s

@@ -18,6 +18,20 @@
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zihintpause < %s \
 # RUN:     | llvm-objdump --mattr=+zihintpause -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+#
+# pause is always available even without Zihintpause
+# (riscv-non-isa/riscv-elf-psabi-doc#474).
+#
+# RUN: llvm-mc %s -triple=riscv32 -M no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv32 \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d -r -M no-aliases - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
 
 # CHECK-S-OBJ-NOALIAS: fence w, 0
 # CHECK-S-OBJ: pause