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[PowerPC] Rename fp/int conversion nodes #67303

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121 changes: 57 additions & 64 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1668,14 +1668,18 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
case PPCISD::FSEL: return "PPCISD::FSEL";
case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
case PPCISD::XSMINC: return "PPCISD::XSMINC";
case PPCISD::FCFID: return "PPCISD::FCFID";
case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
case PPCISD::SINT_TO_FP_INREG:
return "PPCISD::SINT_TO_FP_INREG";
case PPCISD::UINT_TO_FP_INREG:
return "PPCISD::UINT_TO_FP_INREG";
case PPCISD::FP_TO_I64_INREG:
return "PPCISD::FP_TO_I64_INREG";
case PPCISD::FP_TO_I32_INREG:
return "PPCISD::FP_TO_I32_INREG";
case PPCISD::FP_TO_U64_INREG:
return "PPCISD::FP_TO_U64_INREG";
case PPCISD::FP_TO_U32_INREG:
return "PPCISD::FP_TO_U32_INREG";
case PPCISD::FRE: return "PPCISD::FRE";
case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
case PPCISD::FTSQRT:
Expand Down Expand Up @@ -1810,22 +1814,18 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
case PPCISD::STRICT_FADDRTZ:
return "PPCISD::STRICT_FADDRTZ";
case PPCISD::STRICT_FCTIDZ:
return "PPCISD::STRICT_FCTIDZ";
case PPCISD::STRICT_FCTIWZ:
return "PPCISD::STRICT_FCTIWZ";
case PPCISD::STRICT_FCTIDUZ:
return "PPCISD::STRICT_FCTIDUZ";
case PPCISD::STRICT_FCTIWUZ:
return "PPCISD::STRICT_FCTIWUZ";
case PPCISD::STRICT_FCFID:
return "PPCISD::STRICT_FCFID";
case PPCISD::STRICT_FCFIDU:
return "PPCISD::STRICT_FCFIDU";
case PPCISD::STRICT_FCFIDS:
return "PPCISD::STRICT_FCFIDS";
case PPCISD::STRICT_FCFIDUS:
return "PPCISD::STRICT_FCFIDUS";
case PPCISD::STRICT_FP_TO_I64_INREG:
return "PPCISD::STRICT_FP_TO_I64_INREG";
case PPCISD::STRICT_FP_TO_I32_INREG:
return "PPCISD::STRICT_FP_TO_I32_INREG";
case PPCISD::STRICT_FP_TO_U64_INREG:
return "PPCISD::STRICT_FP_TO_U64_INREG";
case PPCISD::STRICT_FP_TO_U32_INREG:
return "PPCISD::STRICT_FP_TO_U32_INREG";
case PPCISD::STRICT_SINT_TO_FP_INREG:
return "PPCISD::STRICT_SINT_TO_FP_INREG";
case PPCISD::STRICT_UINT_TO_FP_INREG:
return "PPCISD::STRICT_UINT_TO_FP_INREG";
case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
case PPCISD::STORE_COND:
return "PPCISD::STORE_COND";
Expand Down Expand Up @@ -8168,22 +8168,18 @@ static unsigned getPPCStrictOpcode(unsigned Opc) {
switch (Opc) {
default:
llvm_unreachable("No strict version of this opcode!");
case PPCISD::FCTIDZ:
return PPCISD::STRICT_FCTIDZ;
case PPCISD::FCTIWZ:
return PPCISD::STRICT_FCTIWZ;
case PPCISD::FCTIDUZ:
return PPCISD::STRICT_FCTIDUZ;
case PPCISD::FCTIWUZ:
return PPCISD::STRICT_FCTIWUZ;
case PPCISD::FCFID:
return PPCISD::STRICT_FCFID;
case PPCISD::FCFIDU:
return PPCISD::STRICT_FCFIDU;
case PPCISD::FCFIDS:
return PPCISD::STRICT_FCFIDS;
case PPCISD::FCFIDUS:
return PPCISD::STRICT_FCFIDUS;
case PPCISD::FP_TO_I64_INREG:
return PPCISD::STRICT_FP_TO_I64_INREG;
case PPCISD::FP_TO_I32_INREG:
return PPCISD::STRICT_FP_TO_I32_INREG;
case PPCISD::FP_TO_U64_INREG:
return PPCISD::STRICT_FP_TO_U64_INREG;
case PPCISD::FP_TO_U32_INREG:
return PPCISD::STRICT_FP_TO_U32_INREG;
case PPCISD::SINT_TO_FP_INREG:
return PPCISD::STRICT_SINT_TO_FP_INREG;
case PPCISD::UINT_TO_FP_INREG:
return PPCISD::STRICT_UINT_TO_FP_INREG;
}
}

Expand Down Expand Up @@ -8221,13 +8217,14 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
switch (DestTy.SimpleTy) {
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
case MVT::i32:
Opc = IsSigned ? PPCISD::FCTIWZ
: (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ);
Opc = IsSigned ? PPCISD::FP_TO_I32_INREG
: (Subtarget.hasFPCVT() ? PPCISD::FP_TO_U32_INREG
: PPCISD::FP_TO_I64_INREG);
break;
case MVT::i64:
assert((IsSigned || Subtarget.hasFPCVT()) &&
"i64 FP_TO_UINT is supported only with FPCVT");
Opc = IsSigned ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ;
Opc = IsSigned ? PPCISD::FP_TO_I64_INREG : PPCISD::FP_TO_U64_INREG;
}
EVT ConvTy = Src.getValueType() == MVT::f128 ? MVT::f128 : MVT::f64;
SDValue Conv;
Expand Down Expand Up @@ -8528,8 +8525,8 @@ static SDValue convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG,
// If we have FCFIDS, then use it when converting to single-precision.
// Otherwise, convert to double-precision and then round.
bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT();
unsigned ConvOpc = IsSingle ? (IsSigned ? PPCISD::FCFIDS : PPCISD::FCFIDUS)
: (IsSigned ? PPCISD::FCFID : PPCISD::FCFIDU);
unsigned ConvOpc =
IsSigned ? PPCISD::SINT_TO_FP_INREG : PPCISD::UINT_TO_FP_INREG;
EVT ConvTy = IsSingle ? MVT::f32 : MVT::f64;
if (Op->isStrictFPOpcode()) {
if (!Chain)
Expand Down Expand Up @@ -14469,13 +14466,13 @@ combineElementTruncationToVectorTruncation(SDNode *N,
// This combine happens after legalization so the fp_to_[su]i nodes are
// already converted to PPCSISD nodes.
unsigned FirstConversion = FirstInput.getOperand(0).getOpcode();
if (FirstConversion == PPCISD::FCTIDZ ||
FirstConversion == PPCISD::FCTIDUZ ||
FirstConversion == PPCISD::FCTIWZ ||
FirstConversion == PPCISD::FCTIWUZ) {
if (FirstConversion == PPCISD::FP_TO_I64_INREG ||
FirstConversion == PPCISD::FP_TO_U64_INREG ||
FirstConversion == PPCISD::FP_TO_I32_INREG ||
FirstConversion == PPCISD::FP_TO_U32_INREG) {
bool IsSplat = true;
bool Is32Bit = FirstConversion == PPCISD::FCTIWZ ||
FirstConversion == PPCISD::FCTIWUZ;
bool Is32Bit = FirstConversion == PPCISD::FP_TO_I32_INREG ||
FirstConversion == PPCISD::FP_TO_U32_INREG;
EVT SrcVT = FirstInput.getOperand(0).getValueType();
SmallVector<SDValue, 4> Ops;
EVT TargetVT = N->getValueType(0);
Expand Down Expand Up @@ -14521,8 +14518,8 @@ combineElementTruncationToVectorTruncation(SDNode *N,
}

unsigned Opcode;
if (FirstConversion == PPCISD::FCTIDZ ||
FirstConversion == PPCISD::FCTIWZ)
if (FirstConversion == PPCISD::FP_TO_I64_INREG ||
FirstConversion == PPCISD::FP_TO_I32_INREG)
Opcode = ISD::FP_TO_SINT;
else
Opcode = ISD::FP_TO_UINT;
Expand Down Expand Up @@ -14932,9 +14929,8 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) {
bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
bool DstDouble = Op.getValueType() == MVT::f64;
unsigned ConvOp = Signed ?
(DstDouble ? PPCISD::FCFID : PPCISD::FCFIDS) :
(DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS);
unsigned ConvOp =
Signed ? PPCISD::SINT_TO_FP_INREG : PPCISD::UINT_TO_FP_INREG;
SDValue WidthConst =
DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2,
dl, false);
Expand Down Expand Up @@ -14966,11 +14962,8 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,

// If we have FCFIDS, then use it when converting to single-precision.
// Otherwise, convert to double-precision and then round.
unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
: PPCISD::FCFIDS)
: (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
: PPCISD::FCFID);
unsigned FCFOp = Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::UINT_TO_FP_INREG
: PPCISD::SINT_TO_FP_INREG;
MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
? MVT::f32
: MVT::f64;
Expand All @@ -14989,9 +14982,9 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
return SDValue();
}

unsigned FCTOp =
Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
PPCISD::FCTIDUZ;
unsigned FCTOp = Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT
? PPCISD::FP_TO_I64_INREG
: PPCISD::FP_TO_U64_INREG;

SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
Expand Down
44 changes: 15 additions & 29 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -56,27 +56,15 @@ namespace llvm {
XSMAXC,
XSMINC,

/// FCFID - The FCFID instruction, taking an f64 operand and producing
/// and f64 value containing the FP representation of the integer that
/// was temporarily in the f64 operand.
FCFID,

/// Newer FCFID[US] integer-to-floating-point conversion instructions for
/// unsigned integers and single-precision outputs.
FCFIDU,
FCFIDS,
FCFIDUS,

/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
/// operand, producing an f64 value containing the integer representation
/// of that FP value.
FCTIDZ,
FCTIWZ,

/// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
/// unsigned integers with round toward zero.
FCTIDUZ,
FCTIWUZ,
/// Inplace integer-to-float conversion.
SINT_TO_FP_INREG,
UINT_TO_FP_INREG,

/// Inplace float-to-integer conversion.
FP_TO_I64_INREG,
FP_TO_I32_INREG,
FP_TO_U64_INREG,
FP_TO_U32_INREG,

/// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
/// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
Expand Down Expand Up @@ -476,16 +464,14 @@ namespace llvm {
XXMFACC,

// Constrained conversion from floating point to int
STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
STRICT_FCTIWZ,
STRICT_FCTIDUZ,
STRICT_FCTIWUZ,
STRICT_FP_TO_I64_INREG = ISD::FIRST_TARGET_STRICTFP_OPCODE,
STRICT_FP_TO_I32_INREG,
STRICT_FP_TO_U64_INREG,
STRICT_FP_TO_U32_INREG,

/// Constrained integer-to-floating-point conversion instructions.
STRICT_FCFID,
STRICT_FCFIDU,
STRICT_FCFIDS,
STRICT_FCFIDUS,
STRICT_SINT_TO_FP_INREG,
STRICT_UINT_TO_FP_INREG,

/// Constrained floating point add in round-to-zero mode.
STRICT_FADDRTZ,
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/PowerPC/PPCInstr64Bit.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1800,7 +1800,7 @@ let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1,
Uses = [RM] in { // FPU Operations.
defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB),
"fcfid", "$RST, $RB", IIC_FPGeneral,
[(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64;
[(set f64:$RST, (PPCany_sint_to_fp f64:$RB))]>, isPPC64;
defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB),
"fctid", "$RST, $RB", IIC_FPGeneral,
[]>, isPPC64;
Expand All @@ -1809,23 +1809,23 @@ defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB),
[]>, isPPC64;
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB),
"fctidz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64;
[(set f64:$RST, (PPCany_fp_to_i64 f64:$RB))]>, isPPC64;

defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB),
"fcfidu", "$RST, $RB", IIC_FPGeneral,
[(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64;
[(set f64:$RST, (PPCany_uint_to_fp f64:$RB))]>, isPPC64;
defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB),
"fcfids", "$RST, $RB", IIC_FPGeneral,
[(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64;
[(set f32:$RST, (PPCany_sint_to_fp f64:$RB))]>, isPPC64;
defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB),
"fcfidus", "$RST, $RB", IIC_FPGeneral,
[(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64;
[(set f32:$RST, (PPCany_uint_to_fp f64:$RB))]>, isPPC64;
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiduz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64;
[(set f64:$RST, (PPCany_fp_to_u64 f64:$RB))]>, isPPC64;
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiwuz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;
[(set f64:$RST, (PPCany_fp_to_u32 f64:$RB))]>, isPPC64;
}

// These instructions store a hash computed from the value of the link register
Expand Down
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