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[PowerPC] Handle CALL_RM like CALL for 32-bit ELF #72758

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[PowerPC] Handle CALL_RM like CALL for 32-bit ELF #72758

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6 changes: 3 additions & 3 deletions llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5475,7 +5475,8 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
// generate secure plt code for TLS symbols.
getGlobalBaseReg();
} break;
case PPCISD::CALL: {
case PPCISD::CALL:
case PPCISD::CALL_RM: {
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@chenzheng1030 chenzheng1030 Jan 10, 2024

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Are your targeting this for SPE? SPE should have no floating point instructions? So round mode should not be a concern? For SPE, we may stop generate CALL_RM where it is generated. Note that CALL_RM performs worse than normal CALL even after instruction selection. They are selected to different instructions.

If for other PPC32 targets, the fix looks reasonable to me.

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@brad0 brad0 Jan 10, 2024

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Are your targeting this for SPE?

This is not for SPE.

if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 ||
!TM.isPositionIndependent() || !Subtarget->isSecurePlt() ||
!Subtarget->isTargetELF())
Expand All @@ -5491,8 +5492,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
if (ES->getTargetFlags() == PPCII::MO_PLT)
getGlobalBaseReg();
}
}
break;
} break;

case PPCISD::GlobalBaseReg:
ReplaceNode(N, getGlobalBaseReg());
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21 changes: 21 additions & 0 deletions llvm/test/CodeGen/PowerPC/ppc32-secure-plt-rm.ll
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@@ -0,0 +1,21 @@
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+secure-plt -relocation-model=pic | FileCheck %s
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@ecnelises ecnelises Dec 5, 2023

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Can we use auto generate script for it?


; This variant of ppc32-pic-large.ll checks that a strictfp call sets
; r30 for the secure PLT.

declare void @call_foo()

define void @foo() {
entry:
call void @call_foo() #0
ret void
}

attributes #0 = { strictfp }

!llvm.module.flags = !{!0}
!0 = !{i32 1, !"PIC Level", i32 2}

; CHECK: addis 30, 30, .LTOC-.L0$pb@ha
; CHECK: addi 30, 30, .LTOC-.L0$pb@l
; CHECK: bl call_foo@PLT+32768