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[SelectionDAG] Add more cases for UDIV and SDIV #86452

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[SelectionDAG] Add more cases for UDIV and SDIV #86452

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23 changes: 20 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5857,14 +5857,31 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
return true;
break;
}
case ISD::UDIV:
case ISD::SDIV:
case ISD::UDIV: {
// div exact can only produce a zero if the dividend is zero.
// TODO: For udiv this is also true if Op1 u<= Op0
if (Op->getFlags().hasExact())
return isKnownNeverZero(Op.getOperand(0), Depth + 1);

// If Op0 >= Op1, then the result is at least 1, and therefore not 0.
KnownBits Op0 = computeKnownBits(Op.getOperand(0), Depth + 1);
KnownBits Op1 = computeKnownBits(Op.getOperand(1), Depth + 1);
if (Op0.isStrictlyPositive() && Op1.isStrictlyPositive() &&
KnownBits::uge(Op0, Op1).value_or(false))
return true;
break;
}
case ISD::SDIV: {
// div exact can only produce a zero if the dividend is zero.
if (Op->getFlags().hasExact())
return isKnownNeverZero(Op.getOperand(0), Depth + 1);

KnownBits Op0 = computeKnownBits(Op.getOperand(0), Depth + 1);
KnownBits Op1 = computeKnownBits(Op.getOperand(1), Depth + 1);
if (Op0.isStrictlyPositive() && Op1.isStrictlyPositive() &&
KnownBits::uge(Op0, Op1).value_or(false))
return true;
break;
}
case ISD::ADD:
if (Op->getFlags().hasNoUnsignedWrap())
if (isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
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