[AMDGPU] Add type-generic llvm.amdgcn.readfirstlane2 intrinsic #87334
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jayfoad
commented
Apr 2, 2024
jayfoad
commented
- [AMDGPU] Generate readfirstlane checks
- [AMDGPU] Add type-generic llvm.amdgcn.readfirstlane2 intrinsic
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Prior art: TODO:
This patch tries to legalize readfirstlane2 for all legal types, but it should probably work on illegal types like |
| def int_amdgcn_wave_reduce_umin : AMDGPUWaveReduce; | ||
| def int_amdgcn_wave_reduce_umax : AMDGPUWaveReduce; | ||
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| // i32 llvm.amdgcn.readfirstlane(i32) |
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I think we should just upgrade the intrinsic instead of introducing a new copy
| @@ -1,71 +1,176 @@ | |||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 | |||
| ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope %s | |||
| %x = call float @llvm.amdgcn.readfirstlane2.f32(float %src) | ||
| call void asm sideeffect "; use $0", "s"(float %x) | ||
| ret void | ||
| } |
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Check bfloat, vector bfloat/half, float2, some pointers/pointer vectors
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What is float2? Done the others.
| MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); | ||
| return DAG.getBitcast( | ||
| VT, DAG.getAnyExtOrTrunc( | ||
| DAG.getNode(AMDGPUISD::READFIRSTLANE, DL, MVT::i32, |
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Maybe directly accept legal 32-bit types and avoid the bitcast?
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Superseded by #89217. |
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