[MachineScheduler] Experimental option to partially disable pre-ra scheduling.

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -94,6 +94,7 @@
 #include <cassert>
 #include <llvm/Support/raw_ostream.h>
 #include <memory>
+#include <set>
 #include <string>
 #include <vector>
 
@@ -487,6 +488,11 @@ class ScheduleDAGMILive : public ScheduleDAGMI {
                    MachineBasicBlock::iterator end,
                    unsigned regioninstrs) override;
 
+  bool disableForRegion(MachineBasicBlock *bb,
+                        MachineBasicBlock::iterator begin,
+                        MachineBasicBlock::iterator end,
+                        unsigned regioninstrs) const override;
+
   /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
   /// reorderable instructions.
   void schedule() override;
@@ -1071,7 +1077,7 @@ class GenericSchedulerBase : public MachineSchedStrategy {
   enum CandReason : uint8_t {
     NoCand, Only1, PhysReg, RegExcess, RegCritical, Stall, Cluster, Weak,
     RegMax, ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
-    TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
+    TopDepthReduce, TopPathReduce, NextDefUse, RegPressure, NodeOrder};
 
 #ifndef NDEBUG
   static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
@@ -1208,6 +1214,33 @@ int biasPhysReg(const SUnit *SU, bool isTop);
 /// GenericScheduler shrinks the unscheduled zone using heuristics to balance
 /// the schedule.
 class GenericScheduler : public GenericSchedulerBase {
+  //// Experimental members for OOO scheduling. ////
+
+  // TODO: Integrate with SchedDFSResult class.
+  // SU -> Nodes above in subtree.
+  std::vector<std::set<const SUnit *> > TreeSUs;
+  // SU -> Virtual regs defined above in subtree.
+  std::vector<std::set<Register> > TreeDefs;
+  // SU -> Regs used but not defined above in subtree.
+  std::vector<std::set<Register> > TreeUses;
+
+  // If this SU is non-null, it is the start of a subtree to be scheduled as
+  // a unit.
+  mutable SUnit *NextSubtreeSU = nullptr;
+  // A (small) set of instructions to be scheduled next as a unit.
+  std::set<const SUnit *> NextQueue;
+
+  unsigned DAGHeight;
+  unsigned DAGDepth;
+  unsigned NumScheduled;
+  std::set<Register> LiveRegs; // Currently live registers.
+
+  void initLiveRegs(ScheduleDAGMILive *DAG);
+  void getMIPDiff(const MachineInstr *MI, PressureDiff &PDiff) const;
+  void getTreePDiff(unsigned NodeNum, PressureDiff &PDiff) const;
+  int comparePDiffs(PressureDiff &PDiff1, PressureDiff &PDiff2) const;
+  ////                                          ////
+
 public:
   GenericScheduler(const MachineSchedContext *C):
     GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ"),

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

@@ -319,6 +319,13 @@ namespace llvm {
                              MachineBasicBlock::iterator end,
                              unsigned regioninstrs);
 
+    virtual bool disableForRegion(MachineBasicBlock *bb,
+                                  MachineBasicBlock::iterator begin,
+                                  MachineBasicBlock::iterator end,
+                                  unsigned regioninstrs) const {
+      return false;
+    }
+
     /// Called when the scheduler has finished scheduling the current region.
     virtual void exitRegion();