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Merge pull request #10 from llvm-beanz/user/cbieneman/reland-root-descriptor-fix
Fix setting root descriptor table
2 parents 5ad42b1 + 0ad46db commit c937091

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2 files changed

+65
-7
lines changed

2 files changed

+65
-7
lines changed

lib/API/DX/Device.cpp

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -513,16 +513,13 @@ class DXDevice : public hlsltest::Device {
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uint32_t Inc = Device->GetDescriptorHandleIncrementSize(
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D3D12_DESCRIPTOR_HEAP_TYPE_CBV_SRV_UAV);
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CD3DX12_GPU_DESCRIPTOR_HANDLE Handle{IS.DescHeap->GetGPUDescriptorHandleForHeapStart()};
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uint32_t Offset = 0;
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for (uint32_t Idx = 0; Idx < P.Sets.size(); ++Idx, Offset += Inc) {
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D3D12_GPU_DESCRIPTOR_HANDLE Handle =
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IS.DescHeap->GetGPUDescriptorHandleForHeapStart();
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Handle.ptr += Offset;
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for (uint32_t Idx = 0; Idx < P.Sets.size(); ++Idx) {
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IS.CmdList->SetComputeRootDescriptorTable(Idx, Handle);
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// TODO: This probably computes the wrong offsets if I have multiple
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// descriptor tables in use.
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Handle.Offset(P.Sets[Idx].Resources.size(), Inc);
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}
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IS.CmdList->Dispatch(P.DispatchSize[0], P.DispatchSize[1],
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P.DispatchSize[2]);
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test/Basic/DescriptorSets.test

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
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#--- DescriptorSets.hlsl
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#if defined(__spirv__) || defined(__SPIRV__)
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#define REGISTER(Idx, Space)
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#else
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#define REGISTER(Idx, Space) : register(Idx, Space)
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#endif
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[[vk::binding(0)]] RWBuffer<float4> In REGISTER(u0, space0);
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[[vk::binding(1)]] RWBuffer<float4> Out1 REGISTER(u1, space4);
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[[vk::binding(0,1)]] RWBuffer<float4> Out2 REGISTER(u2, space4);
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[numthreads(1,1,1)]
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void main(uint GI : SV_GroupIndex) {
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Out1[GI] = In[GI] * In[GI];
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Out2[GI] = In[GI] * In[GI] * In[GI];
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}
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//--- DescriptorSets.yaml
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---
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DispatchSize: [1, 1, 1]
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DescriptorSets:
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- Resources:
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- Access: ReadWrite
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Format: Float32
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Channels: 4
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Data: [ 2, 4, 6, 8]
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DirectXBinding:
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Register: 0
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Space: 0
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- Access: ReadWrite
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Format: Float32
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Channels: 4
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ZeroInitSize: 16
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DirectXBinding:
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Register: 1
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Space: 4
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- Resources:
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- Access: ReadWrite
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Format: Float32
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Channels: 4
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ZeroInitSize: 16
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DirectXBinding:
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Register: 2
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Space: 4
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...
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#--- end
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# UNSUPPORTED: Clang
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# RUN: split-file %s %t
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# RUN: %if DirectX %{ dxc -T cs_6_0 -Fo %t.dxil %t/DescriptorSets.hlsl %}
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# RUN: %if DirectX %{ %offloader %t/DescriptorSets.yaml %t.dxil | FileCheck %s %}
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# RUN: %if Vulkan %{ dxc -T cs_6_0 -spirv -fspv-target-env=vulkan1.1 -Fo %t.spv %t/DescriptorSets.hlsl %}
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# RUN: %if Vulkan %{ %offloader %t/DescriptorSets.yaml %t.spv | FileCheck %s %}
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# RUN: %if Metal %{ dxc -T cs_6_0 -Fo %t.dxil %t/DescriptorSets.hlsl %}
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# RUN: %if Metal %{ metal-shaderconverter %t.dxil -o=%t.metallib %}
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# RUN: %if Metal %{ %offloader %t/DescriptorSets.yaml %t.metallib | FileCheck %s %}
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# CHECK: Data:
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# CHECK: Data: [ 4, 16, 36, 64 ]
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# CHECK: Data: [ 8, 64, 216, 512 ]

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