Skip to content

Add tests for asint16 #299

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Aug 12, 2025
Merged
Show file tree
Hide file tree
Changes from 2 commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
67 changes: 67 additions & 0 deletions test/Feature/HLSLLib/asint16.fp16.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
#--- source.hlsl
StructuredBuffer<half4> In0 : register(t0);

RWStructuredBuffer<int16_t4> Out0 : register(u1);


[numthreads(1,1,1)]
void main() {

Out0[0] = asint16(In0[0]);
Out0[1] = int16_t4(asint16(In0[1].xyz), asint16(In0[1].w));
Out0[2] = int16_t4(asint16(In0[2].xy), asint16(In0[2].zw));
Out0[3] = asint16(half4(-5, 0, 10.111, 0.05));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In0
Format: Float16
Stride: 8
Data: [0xc500, 0, 0x490e, 0x2a66, 0xbc00, 0x5640, 0xc500, 0, 0x490e, 0x2a66, 0xbc00, 0x5640]
# [-5, 0, 10.111, 0.05, -1, 100, -5, 0, 10.111, 0.05, -1, 100]
- Name: Out0
Format: Int16
Stride: 8
ZeroInitSize: 32
- Name: ExpectedOut0
Format: Int16
Stride: 8
Data: [ -15104, 0, 18702, 10854, -17408, 22080, -15104, 0, 18702, 10854, -17408, 22080, -15104, 0, 18702, 10854 ]
Results:
- Result: Test0
Rule: BufferExact
Actual: Out0
Expected: ExpectedOut0
DescriptorSets:
- Resources:
- Name: In0
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: Out0
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# https://github.com/llvm/llvm-project/issues/146942
# XFAIL: Clang-Vulkan

# REQUIRES: Int16
# REQUIRES: Half

# RUN: split-file %s %t
# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
98 changes: 98 additions & 0 deletions test/Feature/HLSLLib/asint16.int16.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,98 @@
#--- source.hlsl
StructuredBuffer<int16_t4> In0 : register(t0);
StructuredBuffer<uint16_t4> In1 : register(t1);

RWStructuredBuffer<int16_t4> Out0 : register(u2);
RWStructuredBuffer<int16_t4> Out1 : register(u3);


[numthreads(1,1,1)]
void main() {

Out0[0] = asint16(In0[0]);
Out0[1] = int16_t4(asint16(In0[1].xyz), asint16(In0[1].w));
Out0[2] = int16_t4(asint16(In0[2].xy), asint16(In0[2].zw));
Out0[3] = asint16(int16_t4(0, 32767, -100, -32768));

Out1[0] = asint16(In1[0]);
Out1[1] = int16_t4(asint16(In1[1].xyz), asint16(In1[1].w));
Out1[2] = int16_t4(asint16(In1[2].xy), asint16(In1[2].zw));
Out1[3] = asint16(uint16_t4(0, 100, 65535, 10));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In0
Format: Int16
Stride: 8
Data: [0, 32767, -100, -32768, 10, 20, 30, 6000, -3000, -30000, 50, 60]
- Name: In1
Format: UInt16
Stride: 8
Data: [0, 100, 65535, 10, 20, 30, 40, 50, 60, 70, 80, 6000]
- Name: Out0
Format: Int16
Stride: 8
ZeroInitSize: 32
- Name: ExpectedOut0
Format: Int16
Stride: 8
Data: [0, 32767, -100, -32768, 10, 20, 30, 6000, -3000, -30000, 50, 60, 0, 32767, -100, -32768]
- Name: Out1
Format: Int16
Stride: 8
ZeroInitSize: 32
- Name: ExpectedOut1
Format: Int16
Stride: 8
Data: [ 0, 100, -1, 10, 20, 30, 40, 50, 60, 70, 80, 6000, 0, 100, -1, 10 ]
Results:
- Result: Test0
Rule: BufferExact
Actual: Out0
Expected: ExpectedOut0
- Result: Test1
Rule: BufferExact
Actual: Out1
Expected: ExpectedOut1
DescriptorSets:
- Resources:
- Name: In0
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: In1
Kind: StructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
- Name: Out0
Kind: RWStructuredBuffer
DirectXBinding:
Register: 2
Space: 0
VulkanBinding:
Binding: 2
- Name: Out1
Kind: RWStructuredBuffer
DirectXBinding:
Register: 3
Space: 0
VulkanBinding:
Binding: 3
#--- end

# REQUIRES: Int16
# RUN: split-file %s %t
# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
Loading