Skip to content

add test for fmod #301

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Aug 13, 2025
Merged

add test for fmod #301

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
10b55b2
test for fmod
spall Jul 25, 2025
f536dce
respond to pr comments, fix some values
spall Aug 12, 2025
e2daa73
xfail due to spirv float controls issue
spall Aug 13, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
77 changes: 77 additions & 0 deletions test/Feature/HLSLLib/fmod.16.test
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,77 @@
#--- source.hlsl
StructuredBuffer<half4> In0 : register(t0);
StructuredBuffer<half4> In1 : register(t1);

RWStructuredBuffer<half4> Out0 : register(u2);


[numthreads(1,1,1)]
void main() {

Out0[0] = fmod(In0[0], In1[0]);
Out0[1] = half4(fmod(In0[1].xyz, In1[1].xyz), fmod(In0[1].w, In1[1].w));
Out0[2] = half4(fmod(In0[2].xy, In1[2].xy), fmod(In0[2].zw, In1[2].zw));
Out0[3] = fmod(half4(10.5, -99.5, 5, 0.25), half4(1, -3, 0.25, 5));
}
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit:

Suggested change
Out0[0] = fmod(In0[0], In1[0]);
Out0[1] = half4(fmod(In0[1].xyz, In1[1].xyz), fmod(In0[1].w, In1[1].w));
Out0[2] = half4(fmod(In0[2].xy, In1[2].xy), fmod(In0[2].zw, In1[2].zw));
Out0[3] = fmod(half4(10.5, -99.5, 5, 0.25), half4(1, -3, 0.25, 5));
}
Out0[0] = fmod(In0[0], In1[0]);
Out0[1] = half4(fmod(In0[1].xyz, In1[1].xyz), fmod(In0[1].w, In1[1].w));
Out0[2] = half4(fmod(In0[2].xy, In1[2].xy), fmod(In0[2].zw, In1[2].zw));
Out0[3] = fmod(half4(10.5, -99.5, 5, 0.25), half4(1, -3, 0.25, 5));
}

//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In0
Format: Float16
Stride: 8
Data: [0x4940, 0xd638, 0x4500, 0x3400, 0, 0x6056, 0x4940, 0xd638, 0x4500, 0x3400, 0, 0x6056]
# 10.5, -99.5, 5, 0.25, 0, 555, 10.5, -99.5, 5, 0.25, 0, 555
- Name: In1
Format: Float16
Stride: 8
Data: [0x3c00, 0xc200, 0x3400, 0x4500, 0x4900, 0x4100, 0x3c00, 0xc200, 0x3400, 0x4500, 0x4900, 0x4100]
# 1.1, -3, 0.25, 5, 10, 2.5, 1, -3, 0.25, 5, 10, 2.5
- Name: Out0
Format: Float16
Stride: 8
ZeroInitSize: 32
- Name: ExpectedOut0
Format: Float16
Stride: 8
Data: [ 0x3800, 0xB780, 0x0, 0x3400, 0x0, 0x0, 0x3800, 0xB780, 0x0, 0x3400, 0x0, 0x0, 0x3800, 0xB800, 0x0, 0x3400 ]
# 0.5, -0.46875, 0, 0.25, 0, 0, 0.5 -0.46875, 0, 0.25, 0, 0, 0.5, -0.46875, 0, 0.25
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I expected 10.5 mod 1.1 to be 0.6, I'm surprised 0.5 is the answer? It also doesn't seem like epsilon is high enough to tolerate this error, I'm surprised this is passing.
Also shocked at how far off -99.5 mod -3 is from .5, should we add -Gis to the compilation options perhaps to improve precision?

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yeah the comment on the value was wrong, it was 1 not 1.1; Added Gis and have set the reuslt to -.5

Results:
- Result: Test0
Rule: BufferFloatEpsilon
Epsilon: 0.04
Actual: Out0
Expected: ExpectedOut0
DescriptorSets:
- Resources:
- Name: In0
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: In1
Kind: StructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
- Name: Out0
Kind: RWStructuredBuffer
DirectXBinding:
Register: 2
Space: 0
VulkanBinding:
Binding: 2
#--- end

# REQUIRES: Half
# RUN: split-file %s %t
# RUN: %dxc_target -HV 202x -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
74 changes: 74 additions & 0 deletions test/Feature/HLSLLib/fmod.32.test
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
#--- source.hlsl
StructuredBuffer<float4> In0 : register(t0);
StructuredBuffer<float4> In1 : register(t1);

RWStructuredBuffer<float4> Out0 : register(u2);


[numthreads(1,1,1)]
void main() {

Out0[0] = fmod(In0[0], In1[0]);
Out0[1] = float4(fmod(In0[1].xyz, In1[1].xyz), fmod(In0[1].w, In1[1].w));
Out0[2] = float4(fmod(In0[2].xy, In1[2].xy), fmod(In0[2].zw, In1[2].zw));
Out0[3] = fmod(float4(10.10, -99.99, 5, 0.25), float4(1.1, -3, 0.25, 5));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In0
Format: Float32
Stride: 16
Data: [10.10, -99.99, 5, 0.25, 0, 6555.555, 10.10, -99.99, 5, 0.25, 0, 6555.555]
- Name: In1
Format: Float32
Stride: 16
Data: [1.1, -3, 0.25, 5, 10, 2.22, 1.1, -3, 0.25, 5, 10, 2.22]
- Name: Out0
Format: Float32
Stride: 16
ZeroInitSize: 64
- Name: ExpectedOut0
Format: Float32
Stride: 16
Data: [ 0.2, -0.990005, 0, 0.25, 0, 2.1154, 0.2, -0.990005, 0, 0.25, 0, 2.1154, 0.2, -0.98999, 0, 0.25 ]
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You should be able to remove the ...00005, since epsilon is sufficiently large

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Also -0.98999 is strange, expected -.99

Results:
- Result: Test0
Rule: BufferFloatEpsilon
Epsilon: 0.0008
Actual: Out0
Expected: ExpectedOut0
DescriptorSets:
- Resources:
- Name: In0
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: In1
Kind: StructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
- Name: Out0
Kind: RWStructuredBuffer
DirectXBinding:
Register: 2
Space: 0
VulkanBinding:
Binding: 2
#--- end


# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
Loading