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Acq testbench fix #20

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8 changes: 4 additions & 4 deletions modules/wishbone/wb_acq_core/acq_cnt.vhd
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Expand Up @@ -55,17 +55,17 @@ end acq_cnt;

architecture rtl of acq_cnt is

signal pkt_ct_cnt : unsigned(c_pkt_size_width-1 downto 0);
signal pkt_ct_cnt : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal pkt_cnt_en : std_logic;

signal pkt_ct_cnt_all : std_logic;
signal pkt_ct_cnt_will_finish : std_logic;

signal shots_cnt : unsigned(c_shots_size_width-1 downto 0);
signal shots_cnt : unsigned(c_shots_size_width-1 downto 0) := (others => '0');
signal shots_cnt_all : std_logic;

signal lmt_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0);
signal lmt_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := to_unsigned(1, c_pkt_size_width);
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0) := to_unsigned(1, c_shots_size_width);

begin

Expand Down
20 changes: 10 additions & 10 deletions modules/wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
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Expand Up @@ -198,9 +198,9 @@ architecture rtl of acq_ddr3_axis_write is

-- Flow control signals
signal lmt_pre_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pre_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pre_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pre_pkt_size_aggd_byte_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_aggd_byte : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pos_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
Expand All @@ -212,7 +212,7 @@ architecture rtl of acq_ddr3_axis_write is
signal lmt_full_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_full_pkt_size_aggd_byte_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_aggd_byte : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0);
Expand All @@ -237,7 +237,7 @@ architecture rtl of acq_ddr3_axis_write is
signal fc_dreq_pld : std_logic;
signal fc_ack : std_logic;
signal fc_trigger_cmd : std_logic;
signal fc_data_id_cmd : std_logic_vector(2 downto 0);
signal fc_data_id_cmd : std_logic_vector(2 downto 0) := (others => '0');

signal valid_trans_cmd : std_logic;
signal valid_trans_cmd_d0 : std_logic;
Expand Down Expand Up @@ -267,9 +267,9 @@ architecture rtl of acq_ddr3_axis_write is
signal pl_pkt_thres_hit_pld : std_logic;

-- Counter signals
signal dbg_cmd_pkt_ct_cnt : std_logic_vector(c_pkt_size_width-1 downto 0);
signal dbg_cmd_pkt_ct_cnt : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal dbg_cmd_shots_cnt : std_logic_vector(c_shots_size_width-1 downto 0);
signal dbg_pld_pkt_ct_cnt : std_logic_vector(c_pkt_size_width-1 downto 0);
signal dbg_pld_pkt_ct_cnt : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal dbg_pld_shots_cnt : std_logic_vector(c_shots_size_width-1 downto 0);
signal pl_cmd_cnt_en : std_logic;
signal acq_cmd_cnt_en : std_logic;
Expand All @@ -278,7 +278,7 @@ architecture rtl of acq_ddr3_axis_write is

-- DDR3 Signals
signal ddr_data_in : std_logic_vector(g_ddr_header_width+g_ddr_payload_width-1 downto 0);
signal ddr_addr_cnt_axis : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_addr_cnt_axis : unsigned(g_ddr_addr_width-1 downto 0) := (others => '0');
signal ddr_byte_addr_cnt_axis : std_logic_vector(g_ddr_addr_width-1 downto 0);
signal ddr_addr_cnt_max_reached : std_logic;
signal ddr_addr_cnt_m1_max_reached : std_logic;
Expand All @@ -292,8 +292,8 @@ architecture rtl of acq_ddr3_axis_write is
signal ddr_btt_mem_area_rem : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_btt_slv : std_logic_vector(c_axis_cmd_tdata_btt_width-1 downto 0);
signal ddr_addr_init : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_addr_max : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_addr_max_m1 : unsigned(g_ddr_addr_width-1 downto 0);
signal ddr_addr_max : unsigned(g_ddr_addr_width-1 downto 0) := (others => '0');
signal ddr_addr_max_m1 : unsigned(g_ddr_addr_width-1 downto 0) := (others => '0');
signal ddr_recv_pkt_cnt : unsigned(c_ddr_axis_max_wtt_width-1 downto 0);
signal ddr_addr_first : std_logic;
signal ddr_reissue_trans : std_logic;
Expand Down
34 changes: 17 additions & 17 deletions modules/wishbone/wb_acq_core/acq_fc_fifo.vhd
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Expand Up @@ -246,35 +246,35 @@ architecture rtl of acq_fc_fifo is

-- Samples counts
-- counts the words written in the FIFO
signal fifo_in_valid_cnt : t_fc_pkt;
signal fifo_in_valid_cnt : t_fc_pkt := (others => '0');
signal fifo_in_valid_full : std_logic;

-- Counts the completed tranfered words to ext mem
signal fifo_pkt_sent : std_logic;
signal fifo_pkt_cnt_en : std_logic;
signal fifo_pkt_sent_cnt : t_fc_pkt;
signal fifo_pkt_sent_cnt : t_fc_pkt := (others => '0');
signal fifo_pkt_sent_ct_cnt : t_fc_pkt;
signal fifo_pkt_sent_ct_all : std_logic;
signal acq_cnt_en : std_logic;
signal dbg_pkt_ct_cnt : std_logic_vector(c_pkt_size_width-1 downto 0);
signal dbg_shots_cnt : std_logic_vector(c_shots_size_width-1 downto 0);

-- Transaction limit signals
signal lmt_pre_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pos_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pos_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pos_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_pos_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0);
signal lmt_curr_chan_id : unsigned(c_chan_id_width-1 downto 0);
signal lmt_curr_chan_id_ext : unsigned(c_chan_id_width-1 downto 0);
signal lmt_pre_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pre_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pre_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pre_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pos_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pos_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pos_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pos_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_full_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_full_pkt_size_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_full_pkt_size_alig_s : std_logic_vector(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_full_pkt_size_aggd : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0) := (others => '0');
signal lmt_curr_chan_id : unsigned(c_chan_id_width-1 downto 0) := (others => '0');
signal lmt_curr_chan_id_ext : unsigned(c_chan_id_width-1 downto 0) := (others => '0');
signal lmt_valid : std_logic;
signal lmt_valid_ext : std_logic;

Expand Down
2 changes: 1 addition & 1 deletion modules/wishbone/wb_acq_core/acq_fsm.vhd
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Expand Up @@ -189,7 +189,7 @@ architecture rtl of acq_fsm is
signal post_trig_skip_r : std_logic;
signal post_trig_done_ext : std_logic;
signal samples_cnt : unsigned(c_acq_samples_size-1 downto 0);
signal shots_cnt : unsigned(15 downto 0);
signal shots_cnt : unsigned(15 downto 0) := (others => '0');
signal shots_done : std_logic;
signal shots_decr : std_logic;
signal single_shot : std_logic;
Expand Down
12 changes: 8 additions & 4 deletions modules/wishbone/wb_acq_core/acq_multishot_dpram.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -174,15 +174,17 @@ begin

-- Write through port A
clka_i => fs_clk_i,
bwea_i => open,
bwea_i => (others => '0'),
wea_i => dpram0_wea,
aa_i => dpram0_addra,
da_i => dpram0_dina,
qa_o => open,

-- Read through port B
clkb_i => fs_clk_i,
bweb_i => open,
bweb_i => (others => '0'),
web_i => '0',
db_i => (others => '0'),
ab_i => dpram0_addrb,
qb_o => dpram0_doutb
);
Expand All @@ -201,14 +203,16 @@ begin
rst_n_i => fs_rst_n_i,

clka_i => fs_clk_i,
bwea_i => open,
bwea_i => (others => '0'),
wea_i => dpram1_wea,
aa_i => dpram1_addra,
da_i => dpram1_dina,
qa_o => open,

clkb_i => fs_clk_i,
bweb_i => open,
bweb_i => (others => '0'),
web_i => '0',
db_i => (others => '0'),
ab_i => dpram1_addrb,
qb_o => dpram1_doutb
);
Expand Down
2 changes: 1 addition & 1 deletion modules/wishbone/wb_acq_core/acq_sel_chan.vhd
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Expand Up @@ -62,7 +62,7 @@ end acq_sel_chan;
architecture rtl of acq_sel_chan is

signal lmt_valid : std_logic;
signal lmt_curr_chan_id : unsigned(c_chan_id_width-1 downto 0);
signal lmt_curr_chan_id : unsigned(c_chan_id_width-1 downto 0) := (others => '0');

signal acq_data_marsh_demux : std_logic_vector(c_acq_chan_max_w-1 downto 0);
signal acq_trig_demux : std_logic;
Expand Down
12 changes: 6 additions & 6 deletions modules/wishbone/wb_acq_core/acq_trigger.vhd
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Expand Up @@ -145,12 +145,12 @@ architecture rtl of acq_trigger is
type t_id_pipe is array (natural range <>) of t_acq_id;

-- Signals
signal lmt_dtrig_chan_id : unsigned(c_chan_id_width-1 downto 0);
signal lmt_dtrig_chan_id : unsigned(c_chan_id_width-1 downto 0) := (others => '0');
signal lmt_dtrig_valid : std_logic;
signal lmt_curr_chan_id : unsigned(c_chan_id_width-1 downto 0);
signal lmt_curr_chan_id : unsigned(c_chan_id_width-1 downto 0) := (others => '0');
signal lmt_valid : std_logic;

signal dtrig_data_in : std_logic_vector(g_data_in_width-1 downto 0);
signal dtrig_data_in : std_logic_vector(g_data_in_width-1 downto 0) := (others => '0');
signal dtrig_valid_in : std_logic;
signal dtrig_id_in : t_acq_id;

Expand Down Expand Up @@ -182,8 +182,8 @@ architecture rtl of acq_trigger is
signal int_trig_over_thres : std_logic;
signal int_trig_over_thres_filt : std_logic;
signal int_trig_over_thres_filt_d : std_logic;
signal int_trig_data : std_logic_vector(c_widest_atom_width-1 downto 0);
signal int_trig_data_se : std_logic_vector(c_widest_atom_width-1 downto 0);
signal int_trig_data : std_logic_vector(c_widest_atom_width-1 downto 0) := (others => '0');
signal int_trig_data_se : std_logic_vector(c_widest_atom_width-1 downto 0) := (others => '0');
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal sw_trig : std_logic;
Expand Down Expand Up @@ -314,7 +314,7 @@ begin
-- Problem: Vivado 2015.2 does not support dynamic slicing!
-- Solution: Implement a case statement to address each possible slice

p_int_trig_data : process(acq_num_atoms_uncoalesced_log2)
p_int_trig_data : process(acq_num_atoms_uncoalesced_log2, cfg_int_trig_sel_i, lmt_dtrig_chan_id)
begin
case to_integer(acq_num_atoms_uncoalesced_log2) is
when 0 =>
Expand Down
8 changes: 4 additions & 4 deletions modules/wishbone/wb_acq_core/fc_source.vhd
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Expand Up @@ -122,9 +122,9 @@ architecture rtl of fc_source is
-- signals that a packet was actually transfered
signal pkt_sent : std_logic;
signal lmt_valid : std_logic;
signal lmt_pre_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pos_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_full_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_pre_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_pos_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');
signal lmt_full_pkt_size : unsigned(c_pkt_size_width-1 downto 0) := (others => '0');

-- Pre output FIFO signals
signal pre_out_fifo_we : std_logic;
Expand All @@ -146,7 +146,7 @@ architecture rtl of fc_source is
signal fc_oob_out_int : t_fc_data_oob;

-- Counters
signal fc_in_pend_cnt : t_fc_pkt;
signal fc_in_pend_cnt : t_fc_pkt := (others => '0');

signal output_pipe_full : std_logic;
signal output_pipe_almost_full : std_logic;
Expand Down
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