Production v1.3 (INT PWR AFC4 SDR) release

Production v1.3 release.

Changelog:

• Remove C14 from IC15 +- inputs, connect it to -7V instead;
• Change DAC8831ICRGYT footprint;
• Fix solder paste layer for IC26 and IC27;

Production v1.2 (INT PWR AFC4 SDR) release

Production v1.2 release.

Changelog:

• Update compatible part replacement list;
• Add Rt calculation for setting the LT8362 frequency;
• Update ADP1850 design parameters.

Production v1.2-rc3 (INT PWR AFC4 SDR) Pre-release

Production v1.2 release candidate 3 for review

Changelog:

• Update schematic template;
• Fix sync frequencies comment;
• Don't use 2d shapes in the spreadsheet template;
• Add thermal vias to IC19 GND pad;
• BOM post-processing script;
• Improvements to the BOM template.

Production v1.2-rc2 (INT PWR AFC4 SDR)

Production v1.2 release candidate 2 for review

Changelog:

• Swap R65, R66 with R61, R62 (respectively);
• Small PCB layout improvements;
• Replace EMZL250ARA331MHA0G with 20SVPF390M capacitors;
• Substitute LT8362EDD with LT8364IDE;
• Change IC24 and IC25 PN to TPS7A2401DBVR;
• Change IC12 PN to CDCE906PW;
• Rotate C84, C85, C88 and C89 reduce the path to GND;
• Add 1uF decoupling capacitors to IC24 and IC25 VIN.

Production v1.2-rc1 (INT PWR AFC4 SDR)

Production v1.2 release candidate for review

Changelog:

• Monitor +12_HP voltage
• Increase the pad hole diameter of J1 and J2 to 0.65mm
• Add status LEDs for power rails
• Change loop compensator design for better stability
• Remove output files from project
• Replace J4 with two 8 pins connectors (like J5)
• Don't open generated files nor add them to the project
• Change field name from 'Fitted' to 'Mounted'
• Use spreadsheet template for BOM
• Fix the voltage for VS1, VS2, DAC_REF1 and DAC_REF2 to 3.7V
• Connect the DAC's AGNDF/S pins directly do the ground plane
• Invert ADC differential inputs to make things consistent
• Remove VOUT_L and VOUT_R test points
• Disable outputs from the power amplifiers by default
• scripts/currentloop_design.m: add script to determine current PI parameters
• sel_res_ratio.m: modifications for Matlab compatbility
• adc_noise_plot.m: modifications for Matlab compatbility
• *design.m: replace printf calls by fprintf for MATLAB compatibility
• Set the OPA569 output current limit to 1.1A
• Connect screw plated vias to GND
• ADC noise plot script
• Simplify variant selection for fabrication outputs
• Add 10uF ceramic capacitors to +12V_HP, +VS1 and +VS2 rails
• Add a series resistor before ADP1850 VIN
• Correct I2C address of the CDCE906PW PLL
• Fix hotswap handle mounting hole position

Prototype v1.1 (INT PWR AFC3.1 SDR)

Prototype v1.1 release for manufacturing.

Changelog:

• Replace the NJM11100F1 LDO with TPS7A2401;
• Fix unconnected 3V3 track;
• Fix wrong voltage output from the +3.3V power supply.

Prototype v1.0 (INT PWR AFC3.1 SDR)

Prototype v1.0 release for manufacturing.

Changelog:

• Add ADC DDR / SDR mode variant;
• Variants fixes;
• Add 8 channel variant for AFC3.1 internal power;
• Plate all screw holes;
• Display IC26 and IC27 device names on schematic;

Prototype v1.0-rc3 (INT PWR AFC3.1)

This is the 3rd PCB layout release candidate, variant: INT PWR AFC3.1

Changelog:

• LTC2324: Use the SDOC data line instead of SDOB;
• Update Desy Zone 3 pin assingment recommendation link;
• Add project url and the open hardware logo;
• Move the 220pF capacitors (C87_CHx) near the ADCs;
• Replace C86 with a 47nF C0G 0805 ceramic capacitor.

Prototype v1.0-rc2 (INT PWR AFC3.1)

This is the 2nd PCB layout release candidate, variant: INT PWR AFC3.1

Changelog:

• Change column 'Part Description' to 'Description';
• Separate fabrication outputs by variant;
• Update components from libraries;
• Replace SRN5040TA-4R7M with SRN5040TA-6R8M;
• Replace SML-311UTT86K with HSMC-C190;
• Replace LTC232xIUKG-16 ADCs with LTC232xCUKG-16.

Prototype 1.0 Release Candidate 1

This is the first complete PCB layout release candidate.

Changelog:

• Update OutJob file;
• Update schematic sheet template and parameters;
• Mark all test points and fiducials as not fited;
• Update draftsman;
• Include static sensitive and recycle logos;
• Update Draftsman file;
• Fix Unrouted net DRC violations;
• Add LNLS logo;
• Update R83 footprint to fix DRC errors;
• Adjust solder paste mask expansion;
• Generate gerber files for all cooper layers;
• Ensure low inductance paths for decoupling caps in the ADCs;
• Ignore room violations for some components;
• Remove matched length rule from DIFF100 class;
• Fix silkscreen DRC violations;
• Edit soldermask sliver and hole to hole clearance DRCs;
• Fully routed board;
• Change the order of CLK_DAC and CS_DAC signals;
• Local routing mostly done, patial global routing;
• Fix ADC wrong channel numbering;
• Change the voltage monitoring ADC signal order;
• Swap CH3_L and CH3_H in J4 to the correct order;
• Power amplifiers routing + power distribution;
• Swap GND and +12_EXT signals in J6 to aid routing;
• Finish power supply local routing;
• Add M2 screws to attach the heatsinks;
• C48 should be placed directly after L8;
• Improvements in output stability for -7V and +7V supplys;
• C64 should be placed after L14 in the +7V supply;
• Replace R59 and R60 for 10k resistors.