Fix various typos

doc/02_user/integration.rst

@@ -34,7 +34,7 @@ Primitives
 ----------
 
 Ibex uses a number of primitive modules (that are held outside the :file:`rtl/` which contains the Ibex RTL).
-Full implementations of these primitives are provided in the Ibex repository but implementors may wish to provide their own implementations.
+Full implementations of these primitives are provided in the Ibex repository but implementers may wish to provide their own implementations.
 Some of the primitives are only used for specific Ibex configurations so can be ignored/removed if you're not using one of those configurations.
 
 The mandatory primitives (used by all configurations) are:
@@ -55,7 +55,7 @@ The configuration dependent primitives are:
    Required where ``SecureIbex == 1``.
  * ``prim_onehot_check`` - Checks a onehot signal is correct, for detecting fault injection attacks.
    Required where ``SecureIbex == 1``.
- * ``prim_secded_X`` - Various primitives to encode and decode SECDED (single error correct, double error detect) error detection and correction codes.
+ * ``prim_secded_X`` - Various primitives to encode and decode SECDED (Single Error Correct, Double Error Detect) error detection and correction codes.
    Required where ``SecureIbex == 1``.
 
 Primitives exclusively used by other primitives:
@@ -207,7 +207,7 @@ Parameters
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``ICache``                   | bit                 | 0          | Enable instruction cache instead of prefetch buffer                   |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
-| ``ICacheECC``                | bit                 | 0          | Enable SECDED ECC protection in ICache (if  ICache == 1)              |
+| ``ICacheECC``                | bit                 | 0          | Enable SECDED ECC protection in ICache (if ICache == 1)               |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``ICacheScramble``           | bit                 | 0          | Enabling this parameter replaces tag and data RAMs of ICache with     |
 |                              |                     |            | scrambling RAM primitives.                                            |

doc/03_reference/exception_interrupts.rst

@@ -11,7 +11,7 @@ Interrupts are handled in vectored mode, i.e., the core jumps to the base addres
 Upon executing an MRET instruction, the core jumps to the program counter previously saved in the ``mepc`` CSR and restores ``mstatus``.MPIE to ``mstatus``.MIE.
 
 The base address of the vector table is initialized to the boot address (must be aligned to 256 bytes, i.e., its least significant byte must be 0x00) when the core is booting.
-The base address can be changed after bootup by writing to the ``mtvec`` CSR.
+The base address can be changed after boot-up by writing to the ``mtvec`` CSR.
 For more information, see the :ref:`cs-registers` documentation.
 
 The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte.

doc/03_reference/icache.rst

@@ -64,7 +64,7 @@ The following table describes the available configuration parameters.
 Performance notes
 -----------------
 
-Note that although larger cache line sizes allow for better area efficiency (lower tagram area overhead), there is a performance penalty.
+Note that although larger cache line sizes allow for better area efficiency (lower tag-RAM area overhead), there is a performance penalty.
 When the core branches to an address that is not aligned to the bottom of a cache line (and the request misses in the cache), the I$ will attempt to fetch this address first from the bus.
 The I$ will then fetch the rest of the remaining beats of data in wrapping address order to complete the cache line (in order to allocate it to the cache).
 While these lower addresses are being fetched, the core is starved of data.
@@ -77,7 +77,7 @@ RAM Arrangement
 ---------------
 
 The data RAMs are arranged as ``NumWays`` banks of ``LineSize`` width.
-If ECC is configured, the tag and data banks will be wider to accomodate the extra checkbits.
+If ECC is configured, the tag and data banks will be wider to accommodate the extra checkbits.
 
 Indicative RAM sizes for common configurations are given in the table below:
 

doc/03_reference/performance_counters.rst

@@ -138,7 +138,7 @@ The remaining event selector CSRs are tied to 0, i.e., no events are counted by
 FPGA Targets
 ------------
 
-For FPGA targets the performance counters constitute a particularily large structure.
+For FPGA targets the performance counters constitute a particularly large structure.
 Implementing the maximum 29 event counters 32, 48 and 64 bit wide results in relative logic utilizations of the core of 100%, 111% and 129% respectively.
 The relative numbers of flip-flops are 100%, 125% and 150%.
 It is recommended to implement event counters of 32 bit width where possible.

doc/03_reference/register_file.rst

@@ -28,7 +28,8 @@ FPGA Register File
 
 The FPGA register file leverages synchronous-write / asynchronous-read RAM design elements, where available on FPGA targets.
 
-For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives. Using this design with a Xilinx Artya7-100 FPGA conserves around 600 Logic LUTs and 1000 flip-flops at the expense of 48 LUTRAMs for the 31-entry register file as compared to the flip-flop-based register file.
+For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives.
+Using this design with a Xilinx Arty A7-100 FPGA conserves around 600 Logic LUTs and 1000 flip-flops at the expense of 48 LUTRAMs for the 31-entry register file as compared to the flip-flop-based register file.
 
 This makes it the **first choice for FPGA synthesis**.
 

doc/03_reference/security.rst

@@ -61,7 +61,7 @@ Other values of **dummy_instr_mask** are legal, but will have a less predictable
 
 The interval between instruction insertion is randomized in the core using an LFSR.
 The initial seed and output permutation for this LFSR can be set using parameters from the top-level of Ibex.
-Sofware can periodically re-seed this LFSR with true random numbers (if available) via the **secureseed** CSR.
+Software can periodically re-seed this LFSR with true random numbers (if available) via the **secureseed** CSR.
 This will make the insertion interval of dummy instructions much harder for an attacker to predict.
 
 Note that the dummy instruction feature inserts multiply and divide instructions.

doc/03_reference/verification_stages.rst

@@ -97,7 +97,7 @@ V2 Checklist
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Coverage      | FPV_COI_COVERAGE_V2                 | N/A        | No formal applied for non-security features in Ibex.                                                                                                                 |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| Integration   | PRE_VERIFIED_SUB_MODULES_V2         | Complete   | ICache is verified in a seperate testbench.                                                                                                                          |
+| Integration   | PRE_VERIFIED_SUB_MODULES_V2         | Complete   | ICache is verified in a separate testbench.                                                                                                                          |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Issues        | NO_HIGH_PRIORITY_ISSUES_PENDING     | Complete   |                                                                                                                                                                      |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -178,7 +178,7 @@ The mapping between countermeasures and tests is given below
 |                                | This test produces double faults, which are checked by an assertion.                                                                                                                                                                                                                                       |
 |                                | ``chip_sw_rv_core_ibex_double_fault`` top-level test in OpenTitan demonstrates escalation on a double fault                                                                                                                                                                                                |
 +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| ICACHE.MEM.SCRAMBLE            | No explicit testing, the scrambling memory primitive is seperately verified within OpenTitan.                                                                                                                                                                                                              |
+| ICACHE.MEM.SCRAMBLE            | No explicit testing, the scrambling memory primitive is separately verified within OpenTitan.                                                                                                                                                                                                              |
 |                                | Assertions in the OpenTitan specific ``rv_core_ibex`` wrapper ensure a newly requested scramble key is correctly applied to the scrambling memories.                                                                                                                                                       |
 |                                | The ``rv_core_ibex_icache_invalidate_test`` OpenTitan top-level test covers assertions within the OpenTitan specific ``rv_core_ibex`` wrapper that check that a ``FENCE.I`` results in an icache scramble key request and that the returned key is correctly supplied to the scrambling memory primitives. |
 +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

dv/cosim/spike_cosim.cc

@@ -166,7 +166,7 @@ bool SpikeCosim::backdoor_read_mem(uint32_t addr, size_t len,
 //   The state.last_inst_pc also remains with the sentinel value PC_INVALID.
 // - If we catch a trap_t&, then the take_trap() fn updates the state of the
 //   processor, and when we call step() again we start executing in the new
-//   context of the trap (trap andler, new MSTATUS, debug rom, etc. etc.)
+//   context of the trap (trap handler, new MSTATUS, debug rom, etc. etc.)
 bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
                       bool sync_trap, bool suppress_reg_write) {
   assert(write_reg < 32);
@@ -196,7 +196,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
     // we do the stop, so we can restore it after the step (as spike won't
     // suppressed the register write).
     //
-    // First check retired instruciton to ensure load suppression is correct
+    // First check retired instruction to ensure load suppression is correct
     if (!check_suppress_reg_write(write_reg, pc, suppressed_write_reg)) {
       return false;
     }
@@ -228,7 +228,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
   //    - PC_INVALID == true
   //    - current state is that of the trapping instruction
   // DUT
-  // - If the dut encounters an async trap (which can be thought of as occuring
+  // - If the dut encounters an async trap (which can be thought of as occurring
   //   between instructions), an rvfi_item will be generated for the the first
   //   retired instruction of the trap handler.
   // - If the dut encounters a sync trap, an rvfi_item will be generated for the
@@ -626,7 +626,7 @@ void SpikeCosim::early_interrupt_handle() {
 
 // Ibex splits misaligned accesses into two separate requests. They
 // independently undergo PMP access checks. It is possible for one to fail (so
-// no request produced for that half of the access) whilst the other successed
+// no request produced for that half of the access) whilst the other succeeds
 // (producing a request for that half of the access).
 //
 // Spike splits misaligned accesses up into bytes and will apply PMP access
@@ -1022,7 +1022,7 @@ SpikeCosim::check_mem_result_e SpikeCosim::check_mem_access(
     }
 
     // For any misaligned access that sees an error immediately indicate to
-    // spike the error has occured, so ensure the top pending access gets
+    // spike the error has occurred, so ensure the top pending access gets
     // removed.
     pending_access_done = true;
   }
@@ -1048,7 +1048,7 @@ bool SpikeCosim::pc_is_debug_ebreak(uint32_t pc) {
   uint32_t dcsr = processor->get_csr(CSR_DCSR);
 
   // ebreak debug entry is controlled by the ebreakm (bit 15) and ebreaku (bit
-  // 12) fields of DCSR. If the appropriate bit of the current privlege level
+  // 12) fields of DCSR. If the appropriate bit of the current privilege level
   // isn't set ebreak won't enter debug so return false.
   if ((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0) ||
       (processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0)) {

dv/cosim/spike_cosim.h

@@ -62,7 +62,7 @@ class SpikeCosim : public simif_t, public Cosim {
   uint32_t pending_iside_err_addr;
 
   typedef enum {
-    kCheckMemOk,           // Checks passed and access succeded in RTL
+    kCheckMemOk,           // Checks passed and access succeeded in RTL
     kCheckMemCheckFailed,  // Checks failed
     kCheckMemBusError  // Checks passed, but access generated bus error in RTL
   } check_mem_result_e;

dv/cs_registers/model/base_register.cc

@@ -65,7 +65,7 @@ bool BaseRegister::ProcessTransaction(bool *match, RegisterTransaction *trans) {
     // else if (read_val != trans->csr_rdata) {
     //  std::cout << "MCycle(H) incrementing as expected" << std::endl;
     //}
-    // Don't panic about MCycle(H) incremeting, this is expected behavior as
+    // Don't panic about MCycle(H) incrementing, this is expected behavior as
     // the clock is always running. Silently ignore mismatches for MCycle(H).
   } else if (read_val != trans->csr_rdata) {
     std::cout << "Error, transaction:" << std::endl;

dv/formal/check/top.sv

@@ -80,7 +80,7 @@ module top import ibex_pkg::*; #(
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
   input  logic [14:0]                  irq_fast_i,
-  input  logic                         irq_nm_i,       // non-maskeable interrupt
+  input  logic                         irq_nm_i,       // non-maskable interrupt
 
   // Scrambling Interface
   input  logic                         scramble_key_valid_i,
@@ -435,7 +435,7 @@ assign ex_is_checkable_csr = ~(
 `undef INSTR
 `define INSTR wbexc_decompressed_instr
 
-// Illegal instructions arent checkable unless the relevant specifications are present.
+// Illegal instructions aren't checkable unless the relevant specifications are present.
 logic can_check_illegal;
 assign can_check_illegal = `SPEC_ILLEGAL & `SPEC_CSR & `SPEC_MRET & `SPEC_WFI;
 

dv/formal/spec/main.sail

@@ -13,7 +13,7 @@ main is equivalent to the Sail step function, it has some differences however:
    1. It's difficult to compare IRQ handling, since ibex takes them later than the Sail would. This is OK since it's not really
       fair to enforce that IRQs are handled between any two specific instructions, so long as it is eventually.
    2. The three modes are a useful case analysis we can make. This means that to prove correctness of an I-Type instruction, for example, we
-      can more easily seperate out the check for instruction fetch correctness, which makes things faster and avoids repeated work.
+      can more easily separate out the check for instruction fetch correctness, which makes things faster and avoids repeated work.
 */
 
 union FetchResult = {
@@ -48,7 +48,7 @@ function main(insn_bits, mode) : (bits(32), MainMode) -> MainResult = {
 
   let irq = dispatchInterrupt(cur_privilege);
   let f : FetchResult = altFetch(insn_bits[15..0], insn_bits[31..16]);
-  
+
   let res : MainResult = match mode {
     MAIN_IDEX => {
       match decompress(insn) {

dv/formal/spec/spec_api.sv

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 /*
-This module contains the actual instance of the specification. It's quite ugly. Mostly it's just forwaring things to
+This module contains the actual instance of the specification. It's quite ugly. Mostly it's just forwarding things to
 different names and ignoring registers we don't care about.
 */
 

dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv

@@ -347,7 +347,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
   endfunction : final_phase
 
   // If the UVM_EXIT action is triggered (such as by reaching max_quit_count), this callback is run.
-  // This ensures proper cleanup, such as commiting the logfile to disk.
+  // This ensures proper cleanup, such as committing the logfile to disk.
   function void pre_abort();
     cleanup_cosim();
   endfunction

dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv

@@ -178,7 +178,7 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
   endfunction
 
   // Read a word of DATA_WIDTH bits from addr.
-  // Handle reads fromm uninit memory as follows:
+  // Handle reads from uninit memory as follows:
   // - DMEM : return a random value
   // - IMEM : return {2{C.unimp}}
   protected function logic [DATA_WIDTH-1:0] read(bit [ADDR_WIDTH-1:0] addr,

dv/uvm/core_ibex/common/irq_agent/irq_if.sv

@@ -8,7 +8,7 @@ interface irq_if(input clk);
   logic        irq_timer;
   logic        irq_external;
   logic [14:0] irq_fast;
-  logic        irq_nm;       // non-maskeable interrupt
+  logic        irq_nm;       // non-maskable interrupt
 
   clocking driver_cb @(posedge clk);
     default output negedge;

dv/uvm/core_ibex/directed_tests/README.md

@@ -5,7 +5,7 @@ This directory contains the custom directed tests as well as scripts and headers
 Currently following open source test suites are vendored:
 - [riscv-tests](https://github.com/riscv-software-src/riscv-tests)
 - [riscv-arch-tests](https://github.com/riscv-non-isa/riscv-arch-test)
-- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an opensource [repo](https://github.com/joxie/riscv-isa-sim))
+- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an open-source [repo](https://github.com/joxie/riscv-isa-sim))
 
 ## Generating test list
 

dv/uvm/core_ibex/directed_tests/gen_testlist.py

@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 """
-Generating testlists for following opensource test suites
+Generating testlists for following open-source test suites
     - riscv-tests
     - riscv-arch-tests
     - ePMP directed tests

dv/uvm/core_ibex/env/core_ibex_scoreboard.sv

@@ -71,7 +71,7 @@ class core_ibex_scoreboard extends uvm_scoreboard;
         end
       end
       // Latch the 'double_fault_seen_o' signal to catch the fault.
-      // The single pulse may be receieved sometime before the rvfi_seq_item
+      // The single pulse may be received sometime before the rvfi_seq_item
       // corresponding to the faulting instruction is generated. Hence we
       // latch that pulse when it is seen, and then reset above when the
       // seq_item arrives.