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Fix DSim support #2297
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Fix DSim support #2297
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Update code from upstream repository https://github.com/chipsalliance/riscv-dv to revision 71666ebacd69266b1abb7cdbad5e1897ce5884e6 Signed-off-by: Akash Levy <[email protected]>
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Also, I'll share my DSim setup in case you want to try it out. I'm not using DSim Desktop, I'm using the CLI binaries. You need both Here's my DSim base And here's my ibex |
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Tagging @hcallahan-lowrisc for review |
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This is great, thanks! |
ibex_mem_intf_agent_pkg -> ibex_mem_intf_pkg Use ibex enum values instead of integers Add #0 for dsim to start simulation
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Done! 0314b58 has |
hcallahan-lowrisc
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Thanks for your contribution @akashlevy! It's great to see DSim functional again, and very much appreciated.
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Woo-hoo! |
Continued from #2286:
This PR fixes up Ibex UVM support for DSim simulator. Several things had to be fixed:
ZEROenum constant instead of'0and0for instr enums: dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.svCPUCTRLSTS,SECURESEED) toprivileged_reg_tand replace enum constants intoimplemented_csr[]: vendor/google_riscv-dv/src/riscv_instr_pkg.sv, vendor/google_riscv-dv/euvm/riscv/gen/riscv_instr_pkg.d, dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.svibex_mem_intf_agent_pkg::ADDR_WIDTHandibex_mem_intf_agent_pkg::DATA_WIDTHwithibex_mem_intf_pkg::ADDR_WIDTHandibex_mem_intf_pkg::DATA_WIDTH: dv/uvm/core_ibex/tests/core_ibex_base_test.sv, dv/uvm/core_ibex/tests/core_ibex_test_lib.sv, dv/uvm/core_ibex/tests/core_ibex_vseq.sv#0to allow clock to properly start in dv/uvm/core_ibex/tb/core_ibex_tb_top.svreloc_wordin dv/uvm/core_ibex/scripts/run_instr_gen.pydsim_compile_optswithdsim_optsand apply correct defparams and +defines in util/ibex_config.pyWith these fixes, I was able to get most of the UVM tests running with
SIMULATOR=dsim ITERATIONS=1:Future enhancements:
METADATA-DIRmake variable issue