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[hw,rstmgr,dv] Make cascading SVAs more generic
Signed-off-by: Robert Schilling <[email protected]>
1 parent ddbd8d3 commit 01738ac

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7 files changed

+34
-41
lines changed

7 files changed

+34
-41
lines changed

‎hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv.tpl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,9 @@ for p, cs in parent_child_clks.items():
120120
% endfor
121121
% if len(childless) > 0:
122122
expected_recov_timeout_err[clk_mesr_timeout] = 1;
123+
% if len(multi_children):
123124
end
125+
% endif
124126
% endif
125127
disturb_measured_clock(.clk(clk_mesr_timeout), .enable(1'b0));
126128
end

‎hw/ip_templates/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.tpl‎

Lines changed: 22 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,15 @@
44

55
<%
66
sorted_clks = sorted(list(clk_freqs.keys()))
7-
has_sys_io_div4 = any(d.get('name') == 'sys_io_div4' for d in output_rsts) if output_rsts else False
7+
has_sys_io = any("sys_io" in d.get('name') for d in output_rsts) if output_rsts else False
8+
9+
def preferred_domain():
10+
if "io_div4" in sorted_clks:
11+
return "io_div4"
12+
elif "io" in sorted_clks:
13+
return "io"
14+
else:
15+
assert 0, "No preferred clock available"
816
%>\
917
// This has assertions that check the reset outputs of rstmgr cascade properly.
1018
// This means higher level resets always cause the lower level ones to assert.
@@ -129,10 +137,10 @@ interface rstmgr_cascading_sva_if (
129137

130138
// The AON reset triggers the various POR reset for the different clock domains through
131139
// synchronizers.
132-
// The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
140+
// The current system doesn't have any consumers of domain 1 por_${preferred_domain()}, and thus only domain 0
133141
// cascading is checked here.
134142
`CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
135-
resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
143+
resets_o.rst_por_${preferred_domain()}_n[0], SyncCycles, clk_${preferred_domain()}_i)
136144

137145
// The internal reset is triggered by one of synchronized por.
138146
logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
@@ -154,27 +162,23 @@ interface rstmgr_cascading_sva_if (
154162
// The latter is checked independently in pwrmgr_rstmgr_sva_if.
155163
`CASCADED_ASSERTS(CascadeLcToSys, lc_rst_or_sys_req_n[pd], rst_sys_src_n[pd], SysCycles, clk_i)
156164

157-
% if has_sys_io_div4:
165+
% if has_sys_io:
158166
// Controlled by rst_sys_src_n.
159-
if (pd == rstmgr_pkg::DomainAonSel) begin : gen_sys_io_div4_chk
160-
`CASCADED_ASSERTS(CascadeSysToSysIoDiv4, rst_sys_src_n[pd], resets_o.rst_sys_io_div4_n[pd],
161-
SysCycles, clk_io_div4_i)
167+
if (pd == rstmgr_pkg::DomainAonSel) begin : gen_sys_${preferred_domain()}_chk
168+
`CASCADED_ASSERTS(CascadeSysToSysIoDiv4, rst_sys_src_n[pd], resets_o.rst_sys_${preferred_domain()}_n[pd],
169+
SysCycles, clk_${preferred_domain()}_i)
162170
end
163171
% endif
164172
end
165173

166174
// Aon to POR
167-
`CASCADED_ASSERTS(CascadeEffAonToRstPor, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
168-
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
169-
`CASCADED_ASSERTS(CascadeEffAonToRstPorIo, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
170-
resets_o.rst_por_io_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_i)
171-
`CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
172-
resets_o.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_div2_i)
173-
174-
% if 'usb' in clk_freqs:
175-
`CASCADED_ASSERTS(CascadeEffAonToRstPorUsb, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
176-
resets_o.rst_por_usb_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_usb_i)
177-
% endif
175+
% for clk in sorted_clks:
176+
% if "aon" in clk or "io_div4" in clk:
177+
<% continue %>
178+
% endif
179+
`CASCADED_ASSERTS(CascadeEffAonToRstPor${clk.capitalize()}, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
180+
resets_o.rst_por_${clk + "_" if clk != "main" else ""}n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_${clk}_i)
181+
% endfor
178182

179183
// Controlled by rst_lc_src_n.
180184
`CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],

‎hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,6 @@ class clkmgr_frequency_timeout_vseq extends clkmgr_base_vseq;
8888
`uvm_info(`gfn, $sformatf("Will cause a timeout for clk %0s", clk_mesr_timeout.name()),
8989
UVM_MEDIUM)
9090
expected_recov_timeout_err[clk_mesr_timeout] = 1;
91-
end
9291
disturb_measured_clock(.clk(clk_mesr_timeout), .enable(1'b0));
9392
end
9493
wait_before_read_recov_err_code();

‎hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -125,10 +125,10 @@ interface rstmgr_cascading_sva_if (
125125

126126
// The AON reset triggers the various POR reset for the different clock domains through
127127
// synchronizers.
128-
// The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
128+
// The current system doesn't have any consumers of domain 1 por_io, and thus only domain 0
129129
// cascading is checked here.
130130
`CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
131-
resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
131+
resets_o.rst_por_io_n[0], SyncCycles, clk_io_i)
132132

133133
// The internal reset is triggered by one of synchronized por.
134134
logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
@@ -153,13 +153,10 @@ interface rstmgr_cascading_sva_if (
153153
end
154154

155155
// Aon to POR
156-
`CASCADED_ASSERTS(CascadeEffAonToRstPor, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
157-
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
158156
`CASCADED_ASSERTS(CascadeEffAonToRstPorIo, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
159157
resets_o.rst_por_io_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_i)
160-
`CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
161-
resets_o.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_div2_i)
162-
158+
`CASCADED_ASSERTS(CascadeEffAonToRstPorMain, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
159+
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
163160

164161
// Controlled by rst_lc_src_n.
165162
`CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],

‎hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -915,13 +915,6 @@ module chip_darjeeling_verilator #(
915915
.es_rng_valid_i ( es_rng_valid ),
916916
.es_rng_bit_i ( es_rng_bit ),
917917
.es_rng_fips_o ( es_rng_fips ),
918-
.io_clk_byp_req_o ( io_clk_byp_req ),
919-
.io_clk_byp_ack_i ( io_clk_byp_ack ),
920-
.all_clk_byp_req_o ( all_clk_byp_req ),
921-
.all_clk_byp_ack_i ( all_clk_byp_ack ),
922-
.hi_speed_sel_o ( hi_speed_sel ),
923-
.div_step_down_req_i ( div_step_down_req ),
924-
.calib_rdy_i ( ast_init_done ),
925918

926919
// OTP external voltage
927920
.otp_ext_voltage_h_io ( ),

‎hw/top_earlgrey/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -161,13 +161,12 @@ interface rstmgr_cascading_sva_if (
161161
end
162162

163163
// Aon to POR
164-
`CASCADED_ASSERTS(CascadeEffAonToRstPor, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
165-
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
166164
`CASCADED_ASSERTS(CascadeEffAonToRstPorIo, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
167165
resets_o.rst_por_io_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_i)
168-
`CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
166+
`CASCADED_ASSERTS(CascadeEffAonToRstPorIo_div2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
169167
resets_o.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_div2_i)
170-
168+
`CASCADED_ASSERTS(CascadeEffAonToRstPorMain, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
169+
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
171170
`CASCADED_ASSERTS(CascadeEffAonToRstPorUsb, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
172171
resets_o.rst_por_usb_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_usb_i)
173172

‎hw/top_englishbreakfast/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -161,13 +161,12 @@ interface rstmgr_cascading_sva_if (
161161
end
162162

163163
// Aon to POR
164-
`CASCADED_ASSERTS(CascadeEffAonToRstPor, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
165-
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
166164
`CASCADED_ASSERTS(CascadeEffAonToRstPorIo, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
167165
resets_o.rst_por_io_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_i)
168-
`CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
166+
`CASCADED_ASSERTS(CascadeEffAonToRstPorIo_div2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
169167
resets_o.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_div2_i)
170-
168+
`CASCADED_ASSERTS(CascadeEffAonToRstPorMain, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
169+
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
171170
`CASCADED_ASSERTS(CascadeEffAonToRstPorUsb, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
172171
resets_o.rst_por_usb_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_usb_i)
173172

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