[hw,clkmgr,rtl] Remove unneeded bypass interfaces

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/ip_templates/clkmgr/data/clkmgr.hjson.tpl

@@ -117,6 +117,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
     { name: "CLKMGR.MEAS_CTRL.RECOV_ERR",
       desc: "Frequency and timeout measurements can flag recoverable errors."
     }
+% if len(derived_clks) > 0:
     { name: "CLKMGR.LC_EXTCLK.SPEED",
       desc: "Speed of LC controlled modification of external clock."
     }
@@ -129,6 +130,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
     { name: "CLKMGR.SW_EXTCLK.LOW_SPEED",
       desc: "Software configuration of external clock running at 48 MHz."
     }
+% endif
     { name: "CLKMGR.JITTER.REGWEN",
       desc: "Control modification of clock jitter enable."
     }
@@ -154,6 +156,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
       act:     "req",
       package: "clkmgr_pkg",
     },
+% if len(derived_clks) > 0:
 
     { struct:  "lc_tx",
       type:    "uni",
@@ -217,6 +220,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
       act:     "req",
       package: "lc_ctrl_pkg",
     },
+  % endif
 
     { struct:  "mubi4",
       type:    "uni",
@@ -275,6 +279,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
     { name: "IDLE.INTERSIG.MUBI",
       desc: "Idle inputs are multibit encoded."
     }
+  % if len(derived_clks) > 0:
     { name: "LC_CTRL.INTERSIG.MUBI",
       desc: "The life cycle control signals are multibit encoded."
     }
@@ -287,6 +292,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
     { name: "DIV.INTERSIG.MUBI",
       desc: "Divider step down request is multibit encoded."
     }
+  % endif
     { name: "JITTER.CONFIG.MUBI",
       desc: "The jitter enable configuration is multibit encoded."
     }
@@ -303,6 +309,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
   ]
 
   registers: [
+  % if len(derived_clks) > 0:
     { name: "EXTCLK_CTRL_REGWEN",
       desc: "External clock control write enable",
       swaccess: "rw0c",
@@ -398,6 +405,10 @@ rg_srcs = get_rg_srcs(typed_clocks)
         },
       ]
     },
+    % else:
+    // Skip 3 registers for SW compatibility on the register layout if no derived clocks are in use
+    { reserved: "3" }
+    % endif
 
     { name: "JITTER_REGWEN",
       desc: "Jitter write enable",

hw/ip_templates/clkmgr/data/clkmgr_sec_cm_testplan.hjson renamed to hw/ip_templates/clkmgr/data/clkmgr_sec_cm_testplan.hjson.tpl

@@ -90,6 +90,7 @@
       stage: V2S
       tests: ["clkmgr_idle_intersig_mubi"]
     }
+  % if len(derived_clks) > 0:
     {
       name: sec_cm_lc_ctrl_intersig_mubi
       desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI.
@@ -147,6 +148,7 @@
       stage: V2S
       tests: ["clkmgr_div_intersig_mubi"]
     }
+  % endif
     {
       name: sec_cm_jitter_config_mubi
       desc: '''Verify the countermeasure(s) JITTER.CONFIG.MUBI.

hw/ip_templates/clkmgr/data/clkmgr_testplan.hjson renamed to hw/ip_templates/clkmgr/data/clkmgr_testplan.hjson.tpl

@@ -92,6 +92,7 @@
       stage: V2
       tests: ["clkmgr_trans"]
     }
+  % if len(derived_clks) > 0:
     {
       name: extclk
       desc: '''
@@ -144,6 +145,7 @@
       stage: V2
       tests: ["clkmgr_extclk"]
     }
+  % endif
     {
       name: clk_status
       desc: '''
@@ -270,7 +272,9 @@
       desc: '''This runs random sequences in succession.
 
             Randomly chooses from the following sequences:
+          % if len(derived_clks) > 0:
             - clkmgr_extclk_vseq,
+          % endif
             - clkmgr_frequency_timeout_vseq,
             - clkmgr_frequency_vseq,
             - clkmgr_peri_vseq,
@@ -310,6 +314,7 @@
             but the dvsim coverage flow doesn't yet support arrays.
             '''
     }
+  % if len(derived_clks) > 0:
     {
       name: extclk_cg
       desc: '''
@@ -321,6 +326,7 @@
             collects their cross.
             '''
     }
+  % endif
     {
       name: freq_measure_cg
       desc: '''

hw/ip_templates/clkmgr/doc/theory_of_operation.md.tpl

@@ -204,7 +204,7 @@ There are two occasions where this is required:
 -  Life cycle transition from `RAW` / `TEST_LOCKED*` to `TEST_UNLOCKED*` [states](../../../../ip/lc_ctrl/README.md#clk_byp_req).
 -  Software request for external clocks during normal functional mode.
 
-
+% if len(derived_clks) > 0:
 <%text>#### Life Cycle Requested External Clock</%text>
 
 The life cycle controller only requests the io clock input to be switched.
@@ -264,6 +264,7 @@ This table also assumes that high speed external clock is 96MHz, while low speed
 
 As can be seen from the table, the external clock switch scheme prioritizes the stability of the divided clocks, while allowing the undivided clocks to slow down.
 
+% endif
 
 <%text>### Clock Frequency / Time-out Measurements</%text>
 

hw/ip_templates/clkmgr/dv/README.md.tpl

@@ -108,6 +108,7 @@ They depend on the `clk_hints` CSR, which has a separate bit for each, `main_ip_
 They also depend on the `idle_i` input, which also has a separate multi-bit value for each unit.
 Units are considered busy when their corresponding `idle_i` value is not `mubi_pkg::MuBi4True`, and this prevents its clock turning off until it becomes idle.
 
+% if len(derived_clks) > 0:
 ${"####"} clkmgr_extclk_vseq
 
 The sequence `clkmgr_extclk_vseq` randomizes the stimuli that drive the external clock selection.
@@ -117,6 +118,7 @@ When the external clock is selected and `scanmode_i` is not set to `prim_mubi_pk
 * If `lc_ctrl_byp_req_i` is on, or
 * If `extclk_ctrl.hi_speed_sel` CSR is `prim_mubi_pkg::MuBi4True`, when the selection is enabled by software.
 
+% endif
 ${"####"} clkmgr_frequency_vseq
 
 The sequence `clkmgr_frequency_vseq` randomly programs the frequency measurement for each clock so its measurement is either okay, slow, or fast.
@@ -145,7 +147,9 @@ The following covergroups have been developed to prove that the test intent has
   These are wrapped in class `clkmgr_trans_cg_wrap` and instantiated in `clkmgr_env_cov`.
 * Covergroups for the outcome of each clock measurement.
   These are wrapped in class `freq_measure_cg_wrap` and instantiated in `clkmgr_env_cov`.
+% if len(derived_clks) > 0:
 * Covergroup for the external clock selection logic: `extclk_cg` in `clkmgr_env_cov`.
+% endif
 
 See more detailed description at `hw/top_${topname}/ip_autogen/clkmgr/data/clkmgr_testplan.hjson`.
 

hw/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl

@@ -70,10 +70,12 @@
       name: clkmgr_smoke
       uvm_test_seq: clkmgr_smoke_vseq
     }
+  % if len(derived_clks) > 0:
     {
       name: clkmgr_extclk
       uvm_test_seq: clkmgr_extclk_vseq
     }
+  % endif
     {
       name: clkmgr_frequency
       uvm_test_seq: clkmgr_frequency_vseq
@@ -99,6 +101,7 @@
       uvm_test_seq: clkmgr_trans_vseq
       run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiIdle"]
     }
+  % if len(derived_clks) > 0:
     {
       name: clkmgr_lc_ctrl_intersig_mubi
       uvm_test_seq: clkmgr_extclk_vseq
@@ -119,6 +122,7 @@
       uvm_test_seq: clkmgr_extclk_vseq
       run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiDiv"]
     }
+  % endif
     {
       name: clkmgr_regwen
       uvm_test_seq: clkmgr_regwen_vseq

hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_bind.sv.tpl

@@ -12,6 +12,7 @@ module clkmgr_cov_bind;
   );
 % endfor
 
+% if len(derived_clks) > 0:
   bind clkmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if (
     .rst_ni (rst_ni),
     .val    (lc_hw_debug_en_i)
@@ -37,4 +38,5 @@ module clkmgr_cov_bind;
     .mubi   (div_step_down_req_i)
   );
 
+% endif
 endmodule // clkmgr_cov_bind

hw/ip_templates/clkmgr/dv/env/clkmgr_env_cov.sv.tpl

@@ -114,6 +114,7 @@ class clkmgr_env_cov extends cip_base_env_cov #(
   // These covergroups collect outcomes of clock frequency measurements.
   freq_measure_cg_wrap freq_measure_cg_wrap[${len(rg_srcs)}];
 
+% if len(derived_clks) > 0:
   // This embeded covergroup collects coverage for the external clock functionality.
   covergroup extclk_cg with function sample (
       bit csr_sel, bit csr_low_speed, bit hw_debug_en, bit byp_req, bit scanmode
@@ -127,6 +128,7 @@ class clkmgr_env_cov extends cip_base_env_cov #(
     extclk_cross: cross csr_sel_cp, csr_low_speed_cp, hw_debug_en_cp, byp_req_cp, scanmode_cp;
   endgroup
 
+% endif
   // This collects coverage for recoverable errors.
   covergroup recov_err_cg with function sample (
 % for src in reversed(rg_srcs):
@@ -171,7 +173,9 @@ class clkmgr_env_cov extends cip_base_env_cov #(
       clk_mesr_e clk_mesr = clk_mesr_e'(i);
       freq_measure_cg_wrap[i] = new(clk_mesr.name);
     end
+  % if len(derived_clks) > 0:
     extclk_cg = new();
+  % endif
     recov_err_cg = new();
     fatal_err_cg = new();
   endfunction : new

hw/ip_templates/clkmgr/dv/env/clkmgr_if.sv.tpl

@@ -38,6 +38,7 @@ interface clkmgr_if (
   // scanmode_i == MuBi4True defeats all clock gating.
   prim_mubi_pkg::mubi4_t scanmode_i;
 
+% if len(derived_clks) > 0:
   // Life cycle enables clock bypass functionality.
   lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i;
 
@@ -53,11 +54,14 @@ interface clkmgr_if (
 
   prim_mubi_pkg::mubi4_t div_step_down_req;
 
+% endif
   prim_mubi_pkg::mubi4_t jitter_en_o;
   clkmgr_pkg::clkmgr_out_t clocks_o;
 
   prim_mubi_pkg::mubi4_t calib_rdy;
+% if len(derived_clks) > 0:
   prim_mubi_pkg::mubi4_t hi_speed_sel;
+% endif
 
   // Internal DUT signals.
   // ICEBOX(lowrisc/opentitan#18379): This is a core env component (i.e. reusable entity) that
@@ -94,6 +98,7 @@ interface clkmgr_if (
                              ${target}: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_${target}_val_qs${sep}
 % endfor
                              };
+% if len(derived_clks) > 0:
 
   prim_mubi_pkg::mubi4_t extclk_ctrl_csr_sel;
   always_comb begin
@@ -106,6 +111,7 @@ interface clkmgr_if (
         `CLKMGR_HIER.reg2hw.extclk_ctrl.hi_speed_sel.q);
   end
 
+% endif
   prim_mubi_pkg::mubi4_t jitter_enable_csr;
   always_comb begin
     jitter_enable_csr = prim_mubi_pkg::mubi4_t'(`CLKMGR_HIER.reg2hw.jitter_enable.q);
@@ -147,6 +153,7 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     scanmode_i = value;
   endfunction
 
+% if len(derived_clks) > 0:
   function automatic void update_lc_debug_en(lc_ctrl_pkg::lc_tx_t value);
     lc_hw_debug_en_i = value;
   endfunction
@@ -181,17 +188,24 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     endcase
   endfunction
 
+% endif
   task automatic init(mubi_hintables_t idle, prim_mubi_pkg::mubi4_t scanmode,
+    % if len(derived_clks) > 0:
                       lc_ctrl_pkg::lc_tx_t lc_debug_en = lc_ctrl_pkg::Off,
                       lc_ctrl_pkg::lc_tx_t lc_clk_byp_req = lc_ctrl_pkg::Off,
+    % endif
                       prim_mubi_pkg::mubi4_t calib_rdy = prim_mubi_pkg::MuBi4True);
     `uvm_info("clkmgr_if", "In clkmgr_if init", UVM_MEDIUM)
     update_calib_rdy(calib_rdy);
     update_idle(idle);
+  % if len(derived_clks) > 0:
     update_lc_clk_byp_req(lc_clk_byp_req);
     update_lc_debug_en(lc_debug_en);
+  % endif
     update_scanmode(scanmode);
+  % if len(derived_clks) > 0:
     update_all_clk_byp_ack(prim_mubi_pkg::MuBi4False);
+  % endif
   endtask
 
   // Pipeline signals that go through synchronizers with the target clock domain's clock.
@@ -248,6 +262,7 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     input idle_i;
   endclocking
 
+% if len(derived_clks) > 0:
   // Pipelining and clocking block for external clock bypass. The divisor control is
   // triggered by an ast ack, which goes through synchronizers.
   logic step_down_ff;
@@ -259,14 +274,17 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     end
   end
 
+% endif
   clocking clk_cb @(posedge clk);
     input calib_rdy;
+  % if len(derived_clks) > 0:
     input extclk_ctrl_csr_sel;
     input extclk_ctrl_csr_step_down;
     input lc_hw_debug_en_i;
     input io_clk_byp_req;
     input lc_clk_byp_req;
     input step_down = step_down_ff;
+  % endif
     input jitter_enable_csr;
   endclocking
 

hw/ip_templates/clkmgr/dv/env/clkmgr_scoreboard.sv.tpl

@@ -18,7 +18,9 @@ class clkmgr_scoreboard extends cip_base_scoreboard #(
   `uvm_component_utils(clkmgr_scoreboard)
 
   // local variables
+% if len(derived_clks) > 0:
   logic extclk_ctrl_regwen;
+% endif
   logic measure_ctrl_regwen;
 
   // TLM agent fifos
@@ -39,8 +41,10 @@ class clkmgr_scoreboard extends cip_base_scoreboard #(
   task run_phase(uvm_phase phase);
     super.run_phase(phase);
     fork
+    % if len(derived_clks) > 0:
       monitor_all_clk_byp();
       monitor_io_clk_byp();
+    % endif
       monitor_jitter_en();
       sample_peri_covs();
       sample_trans_covs();
@@ -50,6 +54,7 @@ class clkmgr_scoreboard extends cip_base_scoreboard #(
     join_none
   endtask
 
+% if len(derived_clks) > 0:
   task monitor_all_clk_byp();
     mubi4_t prev_all_clk_byp_req = MuBi4False;
     forever
@@ -95,6 +100,7 @@ class clkmgr_scoreboard extends cip_base_scoreboard #(
       end
   endtask
 
+%  endif
   task monitor_jitter_en();
     fork
       forever
@@ -268,6 +274,7 @@ ${spc}cfg.clkmgr_vif.scanmode_i == MuBi4True);
       "alert_test": begin
         // FIXME
       end
+    % if len(derived_clks) > 0:
       "extclk_ctrl_regwen": begin
         if (addr_phase_write) extclk_ctrl_regwen = item.a_data;
       end
@@ -282,6 +289,7 @@ ${spc}cfg.clkmgr_vif.scanmode_i == MuBi4True);
       "extclk_status": begin
         do_read_check = 1'b0;
       end
+    % endif
       "jitter_regwen": begin
       end
       "jitter_enable": begin
@@ -341,7 +349,9 @@ ${spc}cfg.clkmgr_vif.scanmode_i == MuBi4True);
   virtual function void reset(string kind = "HARD");
     super.reset(kind);
     // reset local fifos queues and variables
+  % if len(derived_clks) > 0:
     extclk_ctrl_regwen  = ral.extclk_ctrl_regwen.get_reset();
+  % endif
     measure_ctrl_regwen = ral.measure_ctrl_regwen.get_reset();
   endfunction