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[darjeeling] Remove derived clocks and use external IO clock
Signed-off-by: Robert Schilling <[email protected]>
1 parent e5056b6 commit b7804ce

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49 files changed

+931
-1366
lines changed

‎hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson‎

Lines changed: 170 additions & 223 deletions
Large diffs are not rendered by default.

‎hw/top_darjeeling/data/top_darjeeling.hjson‎

Lines changed: 66 additions & 72 deletions
Large diffs are not rendered by default.

‎hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,7 @@
1515
//=========================================================
1616
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1]
1717
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1]
18-
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1]
1918
-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1]
20-
-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_n[1]
2119
-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0]
2220
-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_device_n[0]
2321
-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host0_n[0]

‎hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,8 @@
2828

2929
wire clk_main;
3030
clk_rst_if clk_rst_if_main(.clk(clk_main), .rst_n(rst_n));
31-
wire clk_io_div4;
32-
clk_rst_if clk_rst_if_io_div4(.clk(clk_io_div4), .rst_n(rst_n));
31+
wire clk_io;
32+
clk_rst_if clk_rst_if_io(.clk(clk_io), .rst_n(rst_n));
3333

3434
tl_if rv_core_ibex__corei_tl_if(clk_main, rst_n);
3535
tl_if rv_core_ibex__cored_tl_if(clk_main, rst_n);
@@ -80,25 +80,25 @@ tl_if mbx6__core_tl_if(clk_main, rst_n);
8080
tl_if mbx_jtag__core_tl_if(clk_main, rst_n);
8181
tl_if mbx_pcie0__core_tl_if(clk_main, rst_n);
8282
tl_if mbx_pcie1__core_tl_if(clk_main, rst_n);
83-
tl_if uart0_tl_if(clk_io_div4, rst_n);
84-
tl_if i2c0_tl_if(clk_io_div4, rst_n);
85-
tl_if gpio_tl_if(clk_io_div4, rst_n);
86-
tl_if spi_host0_tl_if(clk_io_div4, rst_n);
87-
tl_if spi_device_tl_if(clk_io_div4, rst_n);
88-
tl_if rv_timer_tl_if(clk_io_div4, rst_n);
89-
tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n);
90-
tl_if rstmgr_aon_tl_if(clk_io_div4, rst_n);
91-
tl_if clkmgr_aon_tl_if(clk_io_div4, rst_n);
92-
tl_if pinmux_aon_tl_if(clk_io_div4, rst_n);
93-
tl_if otp_ctrl__core_tl_if(clk_io_div4, rst_n);
94-
tl_if otp_macro__prim_tl_if(clk_io_div4, rst_n);
95-
tl_if lc_ctrl__regs_tl_if(clk_io_div4, rst_n);
96-
tl_if alert_handler_tl_if(clk_io_div4, rst_n);
97-
tl_if sram_ctrl_ret_aon__regs_tl_if(clk_io_div4, rst_n);
98-
tl_if sram_ctrl_ret_aon__ram_tl_if(clk_io_div4, rst_n);
99-
tl_if aon_timer_aon_tl_if(clk_io_div4, rst_n);
100-
tl_if ast_tl_if(clk_io_div4, rst_n);
101-
tl_if soc_dbg_ctrl__core_tl_if(clk_io_div4, rst_n);
83+
tl_if uart0_tl_if(clk_io, rst_n);
84+
tl_if i2c0_tl_if(clk_io, rst_n);
85+
tl_if gpio_tl_if(clk_io, rst_n);
86+
tl_if spi_host0_tl_if(clk_io, rst_n);
87+
tl_if spi_device_tl_if(clk_io, rst_n);
88+
tl_if rv_timer_tl_if(clk_io, rst_n);
89+
tl_if pwrmgr_aon_tl_if(clk_io, rst_n);
90+
tl_if rstmgr_aon_tl_if(clk_io, rst_n);
91+
tl_if clkmgr_aon_tl_if(clk_io, rst_n);
92+
tl_if pinmux_aon_tl_if(clk_io, rst_n);
93+
tl_if otp_ctrl__core_tl_if(clk_io, rst_n);
94+
tl_if otp_macro__prim_tl_if(clk_io, rst_n);
95+
tl_if lc_ctrl__regs_tl_if(clk_io, rst_n);
96+
tl_if alert_handler_tl_if(clk_io, rst_n);
97+
tl_if sram_ctrl_ret_aon__regs_tl_if(clk_io, rst_n);
98+
tl_if sram_ctrl_ret_aon__ram_tl_if(clk_io, rst_n);
99+
tl_if aon_timer_aon_tl_if(clk_io, rst_n);
100+
tl_if ast_tl_if(clk_io, rst_n);
101+
tl_if soc_dbg_ctrl__core_tl_if(clk_io, rst_n);
102102
tl_if mbx0__soc_tl_if(clk_main, rst_n);
103103
tl_if mbx1__soc_tl_if(clk_main, rst_n);
104104
tl_if mbx2__soc_tl_if(clk_main, rst_n);
@@ -112,8 +112,8 @@ tl_if racl_ctrl_tl_if(clk_main, rst_n);
112112
tl_if ac_range_check_tl_if(clk_main, rst_n);
113113
tl_if rv_dm__dbg_tl_if(clk_main, rst_n);
114114
tl_if mbx_jtag__soc_tl_if(clk_main, rst_n);
115-
tl_if lc_ctrl__dmi_tl_if(clk_io_div4, rst_n);
116-
tl_if soc_dbg_ctrl__jtag_tl_if(clk_io_div4, rst_n);
115+
tl_if lc_ctrl__dmi_tl_if(clk_io, rst_n);
116+
tl_if soc_dbg_ctrl__jtag_tl_if(clk_io, rst_n);
117117

118118
initial begin
119119
wait (xbar_mode !== 1'bx);
@@ -130,11 +130,11 @@ initial begin
130130

131131
// bypass clkmgr, force clocks directly
132132
force tb.dut.top_darjeeling.u_xbar_main.clk_main_i = clk_main;
133-
force tb.dut.top_darjeeling.u_xbar_main.clk_fixed_i = clk_io_div4;
134-
force tb.dut.top_darjeeling.u_xbar_peri.clk_peri_i = clk_io_div4;
133+
force tb.dut.top_darjeeling.u_xbar_main.clk_fixed_i = clk_io;
134+
force tb.dut.top_darjeeling.u_xbar_peri.clk_peri_i = clk_io;
135135
force tb.dut.top_darjeeling.u_xbar_mbx.clk_mbx_i = clk_main;
136136
force tb.dut.top_darjeeling.u_xbar_dbg.clk_dbg_i = clk_main;
137-
force tb.dut.top_darjeeling.u_xbar_dbg.clk_peri_i = clk_io_div4;
137+
force tb.dut.top_darjeeling.u_xbar_dbg.clk_peri_i = clk_io;
138138

139139
// bypass rstmgr, force resets directly
140140
force tb.dut.top_darjeeling.u_xbar_main.rst_main_ni = rst_n;
@@ -237,8 +237,8 @@ initial begin
237237

238238
clk_rst_if_main.set_active(.drive_rst_n_val(0));
239239
clk_rst_if_main.set_freq_khz(1000000000 / 1000);
240-
clk_rst_if_io_div4.set_active(.drive_rst_n_val(0));
241-
clk_rst_if_io_div4.set_freq_khz(250000000 / 1000);
240+
clk_rst_if_io.set_active(.drive_rst_n_val(0));
241+
clk_rst_if_io.set_freq_khz(250000000 / 1000);
242242

243243
end
244244
end

‎hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
clock_srcs:
1212
{
1313
clk_dbg_i: main
14-
clk_peri_i: io_div4
14+
clk_peri_i: io
1515
}
1616
clock_group: infra
1717
reset: rst_dbg_ni
@@ -24,14 +24,14 @@
2424
}
2525
rst_peri_ni:
2626
{
27-
name: lc_io_div4
27+
name: lc_io
2828
domain: "0"
2929
}
3030
}
3131
clock_connections:
3232
{
3333
clk_dbg_i: clkmgr_aon_clocks.clk_main_infra
34-
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
34+
clk_peri_i: clkmgr_aon_clocks.clk_io_infra
3535
}
3636
domain:
3737
[

‎hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
clock_srcs:
1212
{
1313
clk_main_i: main
14-
clk_fixed_i: io_div4
14+
clk_fixed_i: io
1515
}
1616
clock_group: infra
1717
reset: rst_main_ni
@@ -24,14 +24,14 @@
2424
}
2525
rst_fixed_ni:
2626
{
27-
name: lc_io_div4
27+
name: lc_io
2828
domain: "0"
2929
}
3030
}
3131
clock_connections:
3232
{
3333
clk_main_i: clkmgr_aon_clocks.clk_main_infra
34-
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
34+
clk_fixed_i: clkmgr_aon_clocks.clk_io_infra
3535
}
3636
domain:
3737
[

‎hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,21 +10,21 @@
1010
name: peri
1111
clock_srcs:
1212
{
13-
clk_peri_i: io_div4
13+
clk_peri_i: io
1414
}
1515
clock_group: infra
1616
reset: rst_peri_ni
1717
reset_connections:
1818
{
1919
rst_peri_ni:
2020
{
21-
name: lc_io_div4
21+
name: lc_io
2222
domain: "0"
2323
}
2424
}
2525
clock_connections:
2626
{
27-
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
27+
clk_peri_i: clkmgr_aon_clocks.clk_io_infra
2828
}
2929
domain:
3030
[

‎hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson‎

Lines changed: 19 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,8 @@
3737
{clock: "clk_main_i", reset: "rst_main_ni"},
3838
{clock: "clk_io_i", reset: "rst_io_ni"},
3939
{clock: "clk_aon_i", reset: "rst_aon_ni"},
40-
{clock: "clk_io_div4_i", reset: "rst_io_div4_ni", internal: true},
4140
{reset: "rst_root_main_ni"},
4241
{reset: "rst_root_io_ni"},
43-
{reset: "rst_root_io_div4_ni"},
4442
]
4543
bus_interfaces: [
4644
{ protocol: "tlul", direction: "device" }
@@ -80,8 +78,8 @@
8078
],
8179

8280
features: [
83-
{ name: "CLKMGR.ENABLE.IO_DIV4",
84-
desc: "Gating of IO_DIV4 peripheral clock."
81+
{ name: "CLKMGR.ENABLE.IO",
82+
desc: "Gating of IO peripheral clock."
8583
}
8684
{ name: "CLKMGR.HINT.AES",
8785
desc: "Gating of AES transactional clock."
@@ -100,8 +98,8 @@
10098
measurements.
10199
'''
102100
}
103-
{ name: "CLKMGR.MEAS_CTRL.IO_DIV4",
104-
desc: "Frequency and timeout measurements of IO_DIV4 clock."
101+
{ name: "CLKMGR.MEAS_CTRL.IO",
102+
desc: "Frequency and timeout measurements of IO clock."
105103
}
106104
{ name: "CLKMGR.MEAS_CTRL.MAIN",
107105
desc: "Frequency and timeout measurements of MAIN clock."
@@ -434,11 +432,11 @@
434432
fields: [
435433
{
436434
bits: "0",
437-
name: "CLK_IO_DIV4_PERI_EN",
435+
name: "CLK_IO_PERI_EN",
438436
resval: 1,
439437
desc: '''
440-
0 CLK_IO_DIV4_PERI is disabled.
441-
1 CLK_IO_DIV4_PERI is enabled.
438+
0 CLK_IO_PERI is disabled.
439+
1 CLK_IO_PERI is enabled.
442440
'''
443441
}
444442
]
@@ -574,19 +572,19 @@
574572
},
575573
]
576574
},
577-
{ name: "IO_DIV4_MEAS_CTRL_EN",
575+
{ name: "IO_MEAS_CTRL_EN",
578576
desc: '''
579577
Enable for measurement control
580578
''',
581579
regwen: "MEASURE_CTRL_REGWEN",
582580
swaccess: "rw",
583581
hwaccess: "hrw",
584-
async: "clk_io_div4_i",
582+
async: "clk_io_i",
585583
fields: [
586584
{
587585
bits: "3:0",
588586
name: "EN",
589-
desc: "Enable measurement for io_div4",
587+
desc: "Enable measurement for io",
590588
mubi: true,
591589
resval: false,
592590
},
@@ -598,32 +596,32 @@
598596
tags: ["excl:CsrAllTests:CsrExclWrite"]
599597
},
600598

601-
{ name: "IO_DIV4_MEAS_CTRL_SHADOWED",
599+
{ name: "IO_MEAS_CTRL_SHADOWED",
602600
desc: '''
603-
Configuration controls for io_div4 measurement.
601+
Configuration controls for io measurement.
604602

605603
The threshold fields are made wider than required (by 1 bit) to ensure
606604
there is room to adjust for measurement inaccuracies.
607605
''',
608606
regwen: "MEASURE_CTRL_REGWEN",
609607
swaccess: "rw",
610608
hwaccess: "hro",
611-
async: "clk_io_div4_i",
609+
async: "clk_io_i",
612610
shadowed: "true",
613611
update_err_alert: "recov_fault",
614612
storage_err_alert: "fatal_fault",
615613
fields: [
616614
{
617615
bits: "8:0",
618616
name: "HI",
619-
desc: "Max threshold for io_div4 measurement",
617+
desc: "Max threshold for io measurement",
620618
resval: "138"
621619
},
622620

623621
{
624622
bits: "17:9",
625623
name: "LO",
626-
desc: "Min threshold for io_div4 measurement",
624+
desc: "Min threshold for io measurement",
627625
resval: "118"
628626
},
629627
]
@@ -697,10 +695,10 @@
697695
},
698696
{
699697
bits: "1",
700-
name: "IO_DIV4_MEASURE_ERR",
698+
name: "IO_MEASURE_ERR",
701699
resval: 0,
702700
desc: '''
703-
io_div4 has encountered a measurement error.
701+
io has encountered a measurement error.
704702
'''
705703
},
706704
{
@@ -713,10 +711,10 @@
713711
},
714712
{
715713
bits: "3",
716-
name: "IO_DIV4_TIMEOUT_ERR",
714+
name: "IO_TIMEOUT_ERR",
717715
resval: 0,
718716
desc: '''
719-
io_div4 has timed out.
717+
io has timed out.
720718
'''
721719
}
722720
{

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