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[clkmgr] Support 0 derived clocks
Signed-off-by: Robert Schilling <[email protected]>
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hw/ip_templates/clkmgr/rtl/clkmgr.sv.tpl

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@@ -148,6 +148,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
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);
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% endfor
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% if len(derived_clks) > 0:
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////////////////////////////////////////////////////
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// Divided clocks
@@ -161,6 +162,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
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% for src_name in derived_clks:
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logic clk_${src_name};
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% endfor
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% endif
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% for src in derived_clks.values():
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@@ -261,6 +263,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
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.alert_tx_o ( alert_tx_o[i] )
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);
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end
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% if len(derived_clks) > 0:
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////////////////////////////////////////////////////
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// Clock bypass request
@@ -292,6 +295,16 @@ rg_srcs = get_rg_srcs(typed_clocks)
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// divider step down controls
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.step_down_acks_i(step_down_acks)
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);
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% else:
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// No bypass as there are no derived clocks
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// Read inputs and tie-off outputs
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logic unused_bypass = ^{lc_clk_byp_req_i, all_clk_byp_ack_i, io_clk_byp_ack_i};
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assign all_clk_byp_req_o = prim_mubi_pkg::MuBi4False;
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assign io_clk_byp_req_o = prim_mubi_pkg::MuBi4False;
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assign all_clkhi_speed_sel_o_byp_req_o = prim_mubi_pkg::MuBi4False;
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% endif
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////////////////////////////////////////////////////
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// Feed through clocks

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