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lines changed Original file line number Diff line number Diff line change @@ -148,6 +148,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
148148 );
149149
150150% endfor
151+ % if len(derived_clks) > 0:
151152
152153 ////////////////////////////////////////////////////
153154 // Divided clocks
@@ -161,6 +162,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
161162% for src_name in derived_clks:
162163 logic clk_${ src_name} ;
163164% endfor
165+ % endif
164166
165167% for src in derived_clks.values():
166168
@@ -261,6 +263,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
261263 .alert_tx_o ( alert_tx_o[i] )
262264 );
263265 end
266+ % if len(derived_clks) > 0:
264267
265268 ////////////////////////////////////////////////////
266269 // Clock bypass request
@@ -292,6 +295,16 @@ rg_srcs = get_rg_srcs(typed_clocks)
292295 // divider step down controls
293296 .step_down_acks_i(step_down_acks)
294297 );
298+ % else:
299+ // No bypass as there are no derived clocks
300+
301+ // Read inputs and tie-off outputs
302+ logic unused_bypass = ^{ lc_clk_byp_req_i, all_clk_byp_ack_i, io_clk_byp_ack_i} ;
303+
304+ assign all_clk_byp_req_o = prim_mubi_pkg::MuBi4False;
305+ assign io_clk_byp_req_o = prim_mubi_pkg::MuBi4False;
306+ assign all_clkhi_speed_sel_o_byp_req_o = prim_mubi_pkg::MuBi4False;
307+ % endif
295308
296309 ////////////////////////////////////////////////////
297310 // Feed through clocks
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