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martin-velayrswarbrick
martin-velay
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rswarbrick
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[acrc,dv] Prepare SCB for checking
- Retrieve register configuration at each register access and store into the ac_range_check_dut_cfg class. - Fix the TLM interface with the unfiltered and filtered TL buses. Signed-off-by: Martin Velay <[email protected]>
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4 files changed

+166
-46
lines changed

4 files changed

+166
-46
lines changed

‎hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,10 @@ endfunction : build_phase
4141
function void ac_range_check_env::connect_phase(uvm_phase phase);
4242
super.connect_phase(phase);
4343
if (cfg.en_scb) begin
44-
tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export);
45-
tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export);
44+
tl_unfilt_agt.monitor.a_chan_port.connect(scoreboard.tl_unfilt_a_chan_fifo.analysis_export);
45+
tl_unfilt_agt.monitor.d_chan_port.connect(scoreboard.tl_unfilt_d_chan_fifo.analysis_export);
46+
tl_filt_agt.monitor.a_chan_port.connect(scoreboard.tl_filt_a_chan_fifo.analysis_export);
47+
tl_filt_agt.monitor.d_chan_port.connect(scoreboard.tl_filt_d_chan_fifo.analysis_export);
4648
end
4749
if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin
4850
virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer;

‎hw/ip_templates/ac_range_check/dv/env/ac_range_check_scoreboard.sv‎

Lines changed: 79 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,13 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
1010
`uvm_component_utils(ac_range_check_scoreboard)
1111

1212
// Local variables
13+
ac_range_check_dut_cfg dut_cfg;
1314

1415
// TLM agent fifos
15-
uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo;
16-
uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo;
16+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_a_chan_fifo;
17+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_d_chan_fifo;
18+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_a_chan_fifo;
19+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_d_chan_fifo;
1720

1821
// Local queues to hold incoming packets pending comparison
1922
tl_seq_item tl_unfilt_q[$];
@@ -27,21 +30,26 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
2730
extern function void check_phase(uvm_phase phase);
2831

2932
// Class specific methods
30-
extern task process_tl_unfilt_fifo();
31-
extern task process_tl_filt_fifo();
33+
extern task process_tl_unfilt_a_chan_fifo();
34+
extern task process_tl_unfilt_d_chan_fifo();
35+
extern task process_tl_filt_a_chan_fifo();
36+
extern task process_tl_filt_d_chan_fifo();
3237
extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
3338
extern function void reset(string kind = "HARD");
3439
endclass : ac_range_check_scoreboard
3540

3641

3742
function ac_range_check_scoreboard::new(string name="", uvm_component parent=null);
3843
super.new(name, parent);
44+
dut_cfg = ac_range_check_dut_cfg::type_id::create("dut_cfg");
3945
endfunction : new
4046

4147
function void ac_range_check_scoreboard::build_phase(uvm_phase phase);
4248
super.build_phase(phase);
43-
tl_unfilt_fifo = new("tl_unfilt_fifo", this);
44-
tl_filt_fifo = new("tl_filt_fifo", this);
49+
tl_unfilt_a_chan_fifo = new("tl_unfilt_a_chan_fifo", this);
50+
tl_unfilt_d_chan_fifo = new("tl_unfilt_d_chan_fifo", this);
51+
tl_filt_a_chan_fifo = new("tl_filt_a_chan_fifo", this);
52+
tl_filt_d_chan_fifo = new("tl_filt_d_chan_fifo", this);
4553
// TODO: remove once support alert checking
4654
do_alert_check = 0;
4755
endfunction : build_phase
@@ -61,8 +69,10 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
6169
fork
6270
begin : main_thread
6371
fork
64-
process_tl_unfilt_fifo();
65-
process_tl_filt_fifo();
72+
process_tl_unfilt_a_chan_fifo();
73+
process_tl_unfilt_d_chan_fifo();
74+
process_tl_filt_a_chan_fifo();
75+
process_tl_filt_d_chan_fifo();
6676
join
6777
wait fork; // To ensure it will be killed only when the reset will occur
6878
end
@@ -75,21 +85,49 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
7585
end
7686
endtask : run_phase
7787

78-
task ac_range_check_scoreboard::process_tl_unfilt_fifo();
88+
task ac_range_check_scoreboard::process_tl_unfilt_a_chan_fifo();
7989
tl_seq_item item;
8090
forever begin
81-
tl_unfilt_fifo.get(item);
82-
`uvm_info(`gfn, $sformatf("received tl_unfilt item:\n%0s", item.sprint()), UVM_HIGH)
91+
tl_unfilt_a_chan_fifo.get(item);
92+
// `uvm_info(`gfn, $sformatf("Received tl_unfilt_a_chan item:\n%0s", item.sprint()), UVM_HIGH)
93+
`uvm_info(`gfn, $sformatf("Received tl_unfilt_a_chan item:\n%0s", item.sprint()), UVM_LOW)
94+
// TODO MVy
95+
// // At this point, the TL transaction should have completed and the response will be in seq.rsp.
96+
// // The fetch was successful if d_error is false.
97+
// `DV_CHECK(!seq.rsp.d_error, "Single TL unfiltered transaction failed")
8398
end
84-
endtask : process_tl_unfilt_fifo
99+
endtask : process_tl_unfilt_a_chan_fifo
85100

86-
task ac_range_check_scoreboard::process_tl_filt_fifo();
101+
task ac_range_check_scoreboard::process_tl_unfilt_d_chan_fifo();
87102
tl_seq_item item;
88103
forever begin
89-
tl_filt_fifo.get(item);
90-
`uvm_info(`gfn, $sformatf("received tl_filt item:\n%0s", item.sprint()), UVM_HIGH)
104+
tl_unfilt_d_chan_fifo.get(item);
105+
// `uvm_info(`gfn, $sformatf("Received tl_unfilt_d_chan item:\n%0s", item.sprint()), UVM_HIGH)
106+
`uvm_info(`gfn, $sformatf("Received tl_unfilt_d_chan item:\n%0s", item.sprint()), UVM_LOW)
107+
// TODO MVy
108+
// // At this point, the TL transaction should have completed and the response will be in seq.rsp.
109+
// // The fetch was successful if d_error is false.
110+
// `DV_CHECK(!seq.rsp.d_error, "Single TL unfiltered transaction failed")
91111
end
92-
endtask : process_tl_filt_fifo
112+
endtask : process_tl_unfilt_d_chan_fifo
113+
114+
task ac_range_check_scoreboard::process_tl_filt_a_chan_fifo();
115+
tl_seq_item item;
116+
forever begin
117+
tl_filt_a_chan_fifo.get(item);
118+
// `uvm_info(`gfn, $sformatf("Received tl_filt_a_chan item:\n%0s", item.sprint()), UVM_HIGH)
119+
`uvm_info(`gfn, $sformatf("Received tl_filt_a_chan item:\n%0s", item.sprint()), UVM_LOW)
120+
end
121+
endtask : process_tl_filt_a_chan_fifo
122+
123+
task ac_range_check_scoreboard::process_tl_filt_d_chan_fifo();
124+
tl_seq_item item;
125+
forever begin
126+
tl_filt_d_chan_fifo.get(item);
127+
// `uvm_info(`gfn, $sformatf("Received tl_filt_d_chan item:\n%0s", item.sprint()), UVM_HIGH)
128+
`uvm_info(`gfn, $sformatf("Received tl_filt_d_chan item:\n%0s", item.sprint()), UVM_LOW)
129+
end
130+
endtask : process_tl_filt_d_chan_fifo
93131

94132
task ac_range_check_scoreboard::process_tl_access(tl_seq_item item,
95133
tl_channels_e channel,
@@ -100,7 +138,7 @@ task ac_range_check_scoreboard::process_tl_access(tl_seq_item item,
100138
bit do_read_check = 1'b1;
101139
bit write = item.is_write();
102140
uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr);
103-
tl_phase_e tl_phase;
141+
tl_phase_e tl_phase;
104142

105143
if (!write && channel == AddrChannel) tl_phase = AddrRead;
106144
if ( write && channel == AddrChannel) tl_phase = AddrWrite;
@@ -170,16 +208,36 @@ task ac_range_check_scoreboard::process_tl_access(tl_seq_item item,
170208
// FIXME TODO MVy
171209
end
172210
"range_base": begin
173-
// FIXME TODO MVy
211+
if (tl_phase == AddrWrite) begin
212+
dut_cfg.range_base[csr_idx] = `gmv(ral.range_base[csr_idx]);
213+
end
174214
end
175215
"range_limit": begin
176-
// FIXME TODO MVy
216+
if (tl_phase == AddrWrite) begin
217+
dut_cfg.range_limit[csr_idx] = `gmv(ral.range_limit[csr_idx]);
218+
end
177219
end
178220
"range_perm": begin
179-
// FIXME TODO MVy
221+
if (tl_phase == AddrWrite) begin
222+
dut_cfg.range_perm[csr_idx].log_denied_access =
223+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].log_denied_access));
224+
dut_cfg.range_perm[csr_idx].execute_access =
225+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].execute_access));
226+
dut_cfg.range_perm[csr_idx].write_access =
227+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].write_access));
228+
dut_cfg.range_perm[csr_idx].read_access =
229+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].read_access));
230+
dut_cfg.range_perm[csr_idx].enable =
231+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].enable));
232+
end
180233
end
181234
"range_racl_policy_shadowed": begin
182-
// FIXME TODO MVy
235+
if (tl_phase == AddrWrite) begin
236+
dut_cfg.range_racl_policy[csr_idx].read_perm =
237+
`gmv(ral.range_racl_policy_shadowed[csr_idx].read_perm);
238+
dut_cfg.range_racl_policy[csr_idx].write_perm =
239+
`gmv(ral.range_racl_policy_shadowed[csr_idx].write_perm);
240+
end
183241
end
184242
default: begin
185243
`uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))

‎hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,10 @@ endfunction : build_phase
4141
function void ac_range_check_env::connect_phase(uvm_phase phase);
4242
super.connect_phase(phase);
4343
if (cfg.en_scb) begin
44-
tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export);
45-
tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export);
44+
tl_unfilt_agt.monitor.a_chan_port.connect(scoreboard.tl_unfilt_a_chan_fifo.analysis_export);
45+
tl_unfilt_agt.monitor.d_chan_port.connect(scoreboard.tl_unfilt_d_chan_fifo.analysis_export);
46+
tl_filt_agt.monitor.a_chan_port.connect(scoreboard.tl_filt_a_chan_fifo.analysis_export);
47+
tl_filt_agt.monitor.d_chan_port.connect(scoreboard.tl_filt_d_chan_fifo.analysis_export);
4648
end
4749
if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin
4850
virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer;

‎hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv‎

Lines changed: 79 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,13 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
1010
`uvm_component_utils(ac_range_check_scoreboard)
1111

1212
// Local variables
13+
ac_range_check_dut_cfg dut_cfg;
1314

1415
// TLM agent fifos
15-
uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo;
16-
uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo;
16+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_a_chan_fifo;
17+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_d_chan_fifo;
18+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_a_chan_fifo;
19+
uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_d_chan_fifo;
1720

1821
// Local queues to hold incoming packets pending comparison
1922
tl_seq_item tl_unfilt_q[$];
@@ -27,21 +30,26 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
2730
extern function void check_phase(uvm_phase phase);
2831

2932
// Class specific methods
30-
extern task process_tl_unfilt_fifo();
31-
extern task process_tl_filt_fifo();
33+
extern task process_tl_unfilt_a_chan_fifo();
34+
extern task process_tl_unfilt_d_chan_fifo();
35+
extern task process_tl_filt_a_chan_fifo();
36+
extern task process_tl_filt_d_chan_fifo();
3237
extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
3338
extern function void reset(string kind = "HARD");
3439
endclass : ac_range_check_scoreboard
3540

3641

3742
function ac_range_check_scoreboard::new(string name="", uvm_component parent=null);
3843
super.new(name, parent);
44+
dut_cfg = ac_range_check_dut_cfg::type_id::create("dut_cfg");
3945
endfunction : new
4046

4147
function void ac_range_check_scoreboard::build_phase(uvm_phase phase);
4248
super.build_phase(phase);
43-
tl_unfilt_fifo = new("tl_unfilt_fifo", this);
44-
tl_filt_fifo = new("tl_filt_fifo", this);
49+
tl_unfilt_a_chan_fifo = new("tl_unfilt_a_chan_fifo", this);
50+
tl_unfilt_d_chan_fifo = new("tl_unfilt_d_chan_fifo", this);
51+
tl_filt_a_chan_fifo = new("tl_filt_a_chan_fifo", this);
52+
tl_filt_d_chan_fifo = new("tl_filt_d_chan_fifo", this);
4553
// TODO: remove once support alert checking
4654
do_alert_check = 0;
4755
endfunction : build_phase
@@ -61,8 +69,10 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
6169
fork
6270
begin : main_thread
6371
fork
64-
process_tl_unfilt_fifo();
65-
process_tl_filt_fifo();
72+
process_tl_unfilt_a_chan_fifo();
73+
process_tl_unfilt_d_chan_fifo();
74+
process_tl_filt_a_chan_fifo();
75+
process_tl_filt_d_chan_fifo();
6676
join
6777
wait fork; // To ensure it will be killed only when the reset will occur
6878
end
@@ -75,21 +85,49 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
7585
end
7686
endtask : run_phase
7787

78-
task ac_range_check_scoreboard::process_tl_unfilt_fifo();
88+
task ac_range_check_scoreboard::process_tl_unfilt_a_chan_fifo();
7989
tl_seq_item item;
8090
forever begin
81-
tl_unfilt_fifo.get(item);
82-
`uvm_info(`gfn, $sformatf("received tl_unfilt item:\n%0s", item.sprint()), UVM_HIGH)
91+
tl_unfilt_a_chan_fifo.get(item);
92+
// `uvm_info(`gfn, $sformatf("Received tl_unfilt_a_chan item:\n%0s", item.sprint()), UVM_HIGH)
93+
`uvm_info(`gfn, $sformatf("Received tl_unfilt_a_chan item:\n%0s", item.sprint()), UVM_LOW)
94+
// TODO MVy
95+
// // At this point, the TL transaction should have completed and the response will be in seq.rsp.
96+
// // The fetch was successful if d_error is false.
97+
// `DV_CHECK(!seq.rsp.d_error, "Single TL unfiltered transaction failed")
8398
end
84-
endtask : process_tl_unfilt_fifo
99+
endtask : process_tl_unfilt_a_chan_fifo
85100

86-
task ac_range_check_scoreboard::process_tl_filt_fifo();
101+
task ac_range_check_scoreboard::process_tl_unfilt_d_chan_fifo();
87102
tl_seq_item item;
88103
forever begin
89-
tl_filt_fifo.get(item);
90-
`uvm_info(`gfn, $sformatf("received tl_filt item:\n%0s", item.sprint()), UVM_HIGH)
104+
tl_unfilt_d_chan_fifo.get(item);
105+
// `uvm_info(`gfn, $sformatf("Received tl_unfilt_d_chan item:\n%0s", item.sprint()), UVM_HIGH)
106+
`uvm_info(`gfn, $sformatf("Received tl_unfilt_d_chan item:\n%0s", item.sprint()), UVM_LOW)
107+
// TODO MVy
108+
// // At this point, the TL transaction should have completed and the response will be in seq.rsp.
109+
// // The fetch was successful if d_error is false.
110+
// `DV_CHECK(!seq.rsp.d_error, "Single TL unfiltered transaction failed")
91111
end
92-
endtask : process_tl_filt_fifo
112+
endtask : process_tl_unfilt_d_chan_fifo
113+
114+
task ac_range_check_scoreboard::process_tl_filt_a_chan_fifo();
115+
tl_seq_item item;
116+
forever begin
117+
tl_filt_a_chan_fifo.get(item);
118+
// `uvm_info(`gfn, $sformatf("Received tl_filt_a_chan item:\n%0s", item.sprint()), UVM_HIGH)
119+
`uvm_info(`gfn, $sformatf("Received tl_filt_a_chan item:\n%0s", item.sprint()), UVM_LOW)
120+
end
121+
endtask : process_tl_filt_a_chan_fifo
122+
123+
task ac_range_check_scoreboard::process_tl_filt_d_chan_fifo();
124+
tl_seq_item item;
125+
forever begin
126+
tl_filt_d_chan_fifo.get(item);
127+
// `uvm_info(`gfn, $sformatf("Received tl_filt_d_chan item:\n%0s", item.sprint()), UVM_HIGH)
128+
`uvm_info(`gfn, $sformatf("Received tl_filt_d_chan item:\n%0s", item.sprint()), UVM_LOW)
129+
end
130+
endtask : process_tl_filt_d_chan_fifo
93131

94132
task ac_range_check_scoreboard::process_tl_access(tl_seq_item item,
95133
tl_channels_e channel,
@@ -100,7 +138,7 @@ task ac_range_check_scoreboard::process_tl_access(tl_seq_item item,
100138
bit do_read_check = 1'b1;
101139
bit write = item.is_write();
102140
uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr);
103-
tl_phase_e tl_phase;
141+
tl_phase_e tl_phase;
104142

105143
if (!write && channel == AddrChannel) tl_phase = AddrRead;
106144
if ( write && channel == AddrChannel) tl_phase = AddrWrite;
@@ -170,16 +208,36 @@ task ac_range_check_scoreboard::process_tl_access(tl_seq_item item,
170208
// FIXME TODO MVy
171209
end
172210
"range_base": begin
173-
// FIXME TODO MVy
211+
if (tl_phase == AddrWrite) begin
212+
dut_cfg.range_base[csr_idx] = `gmv(ral.range_base[csr_idx]);
213+
end
174214
end
175215
"range_limit": begin
176-
// FIXME TODO MVy
216+
if (tl_phase == AddrWrite) begin
217+
dut_cfg.range_limit[csr_idx] = `gmv(ral.range_limit[csr_idx]);
218+
end
177219
end
178220
"range_perm": begin
179-
// FIXME TODO MVy
221+
if (tl_phase == AddrWrite) begin
222+
dut_cfg.range_perm[csr_idx].log_denied_access =
223+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].log_denied_access));
224+
dut_cfg.range_perm[csr_idx].execute_access =
225+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].execute_access));
226+
dut_cfg.range_perm[csr_idx].write_access =
227+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].write_access));
228+
dut_cfg.range_perm[csr_idx].read_access =
229+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].read_access));
230+
dut_cfg.range_perm[csr_idx].enable =
231+
mubi4_logic_test_true_strict(`gmv(ral.range_perm[csr_idx].enable));
232+
end
180233
end
181234
"range_racl_policy_shadowed": begin
182-
// FIXME TODO MVy
235+
if (tl_phase == AddrWrite) begin
236+
dut_cfg.range_racl_policy[csr_idx].read_perm =
237+
`gmv(ral.range_racl_policy_shadowed[csr_idx].read_perm);
238+
dut_cfg.range_racl_policy[csr_idx].write_perm =
239+
`gmv(ral.range_racl_policy_shadowed[csr_idx].write_perm);
240+
end
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end
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default: begin
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`uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))

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